| /external/vixl/test/aarch32/traces/ |
| assembler-cond-rdlow-rnlow-rmlow-t32-muls.h | 1 // Copyright 2015, VIXL authors
|
| /external/vixl/test/aarch64/traces/ |
| sim-dup-4s-2opimm-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-sqrshrn-h-2opimm-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-sqrshrun-h-2opimm-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-sqshrn-h-2opimm-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-sqshrun-h-2opimm-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-uqrshrn-h-2opimm-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-uqshrn-h-2opimm-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| /external/vixl/tools/ |
| lint.py | 3 # Copyright 2015, VIXL authors
|
| /art/compiler/optimizing/ |
| codegen_test.cc | 756 // in vixl::aarch64::UseScratchRegisterScope::AcquireNextAvailable,
769 // 3. VIXL requires a third temp register to emit the `Ldr` or
|
| /external/vixl/test/aarch32/config/ |
| data-types.json | 1 // Copyright 2016, VIXL authors
35 // - type: C++ type used by VIXL to represent this operand.
[all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.h | 1 // Copyright 2015, VIXL authors
33 #include "../code-generation-scopes-vixl.h"
34 #include "../globals-vixl.h"
63 namespace vixl { namespace
579 virtual vixl::internal::AssemblerBase* AsAssemblerBase() VIXL_OVERRIDE {
[all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-operand-const-a32-can-use-pc.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-operand-const-a32-cannot-use-pc.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-operand-imm16-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-rn-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-in-it-block.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-rn-rm-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-rn-rm-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-rd-rn-rm-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-rd-rn-rm-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-rn-operand-imm12-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
