| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-rn-operand-rm-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rdlow-operand-imm8-t32-in-it-block.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-operand-rn-shift-rs-a32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-operand-rn-shift-rs-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-rn-a32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-rn-operand-const-a32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-rn-operand-const-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-rn-operand-rm-a32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-rn-operand-rm-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-rn-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| /art/compiler/optimizing/ |
| code_generator_vector_arm_vixl.cc | 20 namespace vixl32 = vixl::aarch32;
|
| optimizing_cfi_test_expected.inc | 218 // VIXL emits an extra 2 bytes here for a 32-bit beq as there is no
|
| /art/test/635-checker-arm64-volatile-load-cc/src/ |
| Main.java | 253 // the scratch registers used by the VIXL AArch64 assembler (and to
|
| /external/vixl/test/aarch32/traces/ |
| assembler-cond-rd-operand-rn-t32-cmp.h | 1 // Copyright 2015, VIXL authors
[all...] |
| assembler-cond-rd-operand-rn-t32-identical-low-registers-in-it-block-mvn.h | 1 // Copyright 2015, VIXL authors
|
| assembler-cond-rd-operand-rn-t32-mov.h | 1 // Copyright 2015, VIXL authors
[all...] |
| assembler-cond-rd-rn-operand-rm-t32-rn-is-sp-in-it-block-add.h | 1 // Copyright 2015, VIXL authors
|
