| /external/vixl/test/aarch32/traces/ |
| simulator-cond-rd-rn-rm-a32-ge-sadd16.h | 1 // Copyright 2015, VIXL authors
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| simulator-cond-rd-rn-rm-a32-ge-sadd8.h | 1 // Copyright 2015, VIXL authors
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| simulator-cond-rd-rn-rm-a32-ge-sasx.h | 1 // Copyright 2015, VIXL authors
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| simulator-cond-rd-rn-rm-a32-ge-ssax.h | 1 // Copyright 2015, VIXL authors
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| simulator-cond-rd-rn-rm-a32-ge-ssub16.h | 1 // Copyright 2015, VIXL authors
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| simulator-cond-rd-rn-rm-a32-ge-ssub8.h | 1 // Copyright 2015, VIXL authors
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| simulator-cond-rd-rn-rm-a32-ge-uadd16.h | 1 // Copyright 2015, VIXL authors
|
| simulator-cond-rd-rn-rm-a32-ge-uadd8.h | 1 // Copyright 2015, VIXL authors
|
| simulator-cond-rd-rn-rm-a32-ge-uasx.h | 1 // Copyright 2015, VIXL authors
|
| simulator-cond-rd-rn-rm-a32-ge-usax.h | 1 // Copyright 2015, VIXL authors
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| simulator-cond-rd-rn-rm-a32-ge-usub16.h | 1 // Copyright 2015, VIXL authors
|
| simulator-cond-rd-rn-rm-a32-ge-usub8.h | 1 // Copyright 2015, VIXL authors
|
| simulator-cond-rd-rn-rm-a32-q-qadd.h | 1 // Copyright 2015, VIXL authors
|
| simulator-cond-rd-rn-rm-a32-q-qdadd.h | 1 // Copyright 2015, VIXL authors
|
| simulator-cond-rd-rn-rm-a32-q-qdsub.h | 1 // Copyright 2015, VIXL authors
|
| simulator-cond-rd-rn-rm-a32-q-qsub.h | 1 // Copyright 2015, VIXL authors
|
| simulator-cond-rd-rn-rm-a32-sel-sel.h | 1 // Copyright 2015, VIXL authors
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| simulator-cond-rd-rn-rm-t32-ge-sadd16.h | 1 // Copyright 2015, VIXL authors
|
| simulator-cond-rd-rn-rm-t32-ge-sadd8.h | 1 // Copyright 2015, VIXL authors
|
| simulator-cond-rd-rn-rm-t32-ge-sasx.h | 1 // Copyright 2015, VIXL authors
|
| simulator-cond-rd-rn-rm-t32-ge-ssax.h | 1 // Copyright 2015, VIXL authors
|
| simulator-cond-rd-rn-rm-t32-ge-ssub16.h | 1 // Copyright 2015, VIXL authors
|
| simulator-cond-rd-rn-rm-t32-ge-ssub8.h | 1 // Copyright 2015, VIXL authors
|
| simulator-cond-rd-rn-rm-t32-ge-uadd16.h | 1 // Copyright 2015, VIXL authors
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| simulator-cond-rd-rn-rm-t32-ge-uadd8.h | 1 // Copyright 2015, VIXL authors
|
