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Searched
refs:BIT0
(Results
1 - 25
of
271
) sorted by null
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/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/
Omap3530.h
33
#define PBIASLITEVMODE0
BIT0
Omap3530Uart.h
34
#define UART_FCR_FIFO_ENABLE
BIT0
38
#define UART_LCR_CHAR_LENGTH_8 (BIT1 |
BIT0
)
41
#define UART_MCR_DTR_FORCE_ACTIVE
BIT0
46
#define UART_LSR_RX_FIFO_E_MASK
BIT0
47
#define UART_LSR_RX_FIFO_E_NOT_EMPTY
BIT0
50
// BIT2:
BIT0
Omap3530Timer.h
56
#define TISR_MAT_IT_FLAG_MASK
BIT0
66
#define TISR_MAT_IT_FLAG_CLEAR
BIT0
71
#define TCLR_ST_ON
BIT0
78
#define TIER_MAT_IT_ENABLE
BIT0
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530.h
33
#define PBIASLITEVMODE0
BIT0
Omap3530Uart.h
34
#define UART_FCR_FIFO_ENABLE
BIT0
38
#define UART_LCR_CHAR_LENGTH_8 (BIT1 |
BIT0
)
41
#define UART_MCR_DTR_FORCE_ACTIVE
BIT0
46
#define UART_LSR_RX_FIFO_E_MASK
BIT0
47
#define UART_LSR_RX_FIFO_E_NOT_EMPTY
BIT0
50
// BIT2:
BIT0
Omap3530Timer.h
56
#define TISR_MAT_IT_FLAG_MASK
BIT0
66
#define TISR_MAT_IT_FLAG_CLEAR
BIT0
71
#define TCLR_ST_ON
BIT0
78
#define TIER_MAT_IT_ENABLE
BIT0
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
I2cRegs.h
53
#define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+
BIT0
) // Master Target Address bits
70
#define I2C_REG_RAW_INTR_STAT_RX_UNDER (
BIT0
) // Raw Interrupt Status Register RX Underflow signal status.
81
#define B_I2C_REG_CLR_STOP_DET (
BIT0
) // Clear STOP DET Interrupt Register
83
#define B_I2C_REG_CLR_START_DET (
BIT0
) // Clear START DET Interrupt Register
85
#define B_I2C_REG_ENABLE (
BIT0
) // Enable (1) or disable (0) I2C Controller
88
#define B_I2C_REG_TXFLR (BIT3+BIT2+BIT1+
BIT0
) // Transmit FIFO Level Register bits
90
#define B_I2C_REG_RXFLR (BIT3+BIT2+BIT1+
BIT0
) // Receive FIFO Level Register bits
/device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
I440FxPiix4.h
38
#define PIIX4_PMREGMISC_PMIOSE
BIT0
Virtio.h
103
#define VRING_AVAIL_F_NO_INTERRUPT
BIT0
117
#define VRING_USED_F_NO_NOTIFY
BIT0
137
#define VRING_DESC_F_NEXT
BIT0
// more descriptors in this request
162
#define VSTAT_ACK
BIT0
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
PchRegsRcrb.h
51
#define B_PCH_RCRB_GCS_BILD
BIT0
// BIOS Interface Lock-Down
PchRegsUsb.h
72
#define B_PCH_EHCI_PWR_CNTL_STS_PWR_STS (BIT1 |
BIT0
) // Power State
74
#define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 |
BIT0
) // D3 Hot State
95
#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 |
BIT0
)
96
#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 |
BIT0
)
PchRegsSmbus.h
64
#define B_PCH_SMBUS_PCICMD_IOSE
BIT0
// I/O Space Enable
68
#define B_PCH_SMBUS_BASE_IOSI
BIT0
// IO Space Indicator
86
#define B_PCH_SMBUS_HBSY
BIT0
// Host Busy
102
#define B_PCH_SMBUS_INTREN
BIT0
// Interrupt Enable
109
#define B_PCH_SMBUS_RW_SEL
BIT0
// Direction of the host transfer, 1 = read, 0 = write
124
#define B_PCH_SMBUS_CRCE
BIT0
// CRC Error
128
#define B_PCH_SMBUS_AAC
BIT0
// Automatically Append CRC
133
#define B_PCH_SMBUS_SMLINK0_CUR_STS
BIT0
// Not supported
139
#define B_PCH_SMBUS_SMBCLK_CUR_STS
BIT0
// SMBCLK Current Status
142
#define B_PCH_SMBUS_HOST_NOTIFY_STS
BIT0
// Host Notify Status
[
all
...]
PchRegsSata.h
77
#define B_PCH_SATA_COMMAND_IOSE
BIT0
// I/O Space Enable
96
#define B_PCH_SATA_PI_REGISTER_PNE
BIT0
// Primary Mode Native Enable
117
#define B_PCH_SATA_PCMD_BAR_RTE
BIT0
// Resource Type Indicator
121
#define B_PCH_SATA_PCTL_BAR_RTE
BIT0
// Resource Type Indicator
125
#define B_PCH_SATA_SCMD_BAR_RTE
BIT0
// Resource Type Indicator
129
#define B_PCH_SATA_SCTL_BAR_RTE
BIT0
// Resource Type Indicator
134
#define B_PCH_SATA_LBAR_RTE
BIT0
// Resource Type Indicator
146
#define B_PCH_SATA_ABAR_RTE
BIT0
// Resource Type Indicator
165
#define B_PCH_SATA_PMCS_PS (BIT1 |
BIT0
) // Power State
199
#define B_PCH_SATA_PCS_PORT0_EN
BIT0
// Port 0 Enabled
[
all
...]
PchRegsPcu.h
85
#define B_PCH_LPC_COMMAND_IOSE
BIT0
// I/O Space Enable
142
#define B_PCH_LPC_ACPI_BASE_MEMI
BIT0
// Memory Space Indication
149
#define B_PCH_LPC_PMC_BASE_MEMI
BIT0
// Memory Space Indication
154
#define B_PCH_LPC_GPIO_BASE_MEMI
BIT0
// Memory Space Indication
161
#define B_PCH_LPC_IO_BASE_MEMI
BIT0
// Memory Space Indication
168
#define B_PCH_LPC_ILB_BASE_MEMI
BIT0
// Memory Space Indication
175
#define B_PCH_LPC_SPI_BASE_MEMI
BIT0
// Memory Space Indicator
182
#define B_PCH_LPC_MPHY_BASE_MEMI
BIT0
// Memory Space Indicator
189
#define B_PCH_LPC_PUNIT_BASE_MEMI
BIT0
// Memory Space Indicator
192
#define B_PCH_LPC_UART_CTRL_COM1_EN
BIT0
// COM1 Enable
[
all
...]
PchRegsLpss.h
87
#define B_PCH_LPSS_DMAC_BAR_MS
BIT0
// Message Space
94
#define B_PCH_LPSS_DMAC_BAR1_MS
BIT0
// Message Space
122
#define B_PCH_LPSS_DMAC_PCS_PS (BIT1 |
BIT0
) // Power State
172
#define B_PCH_LPSS_I2C_BAR_MS
BIT0
// Message Space
179
#define B_PCH_LPSS_I2C_BAR1_MS
BIT0
// Message Space
207
#define B_PCH_LPSS_I2C_PCS_PS (BIT1 |
BIT0
) // Power State
218
#define B_PCH_LPSS_I2C_MEM_RESETS_APB
BIT0
// APB Domain Reset
259
#define B_PCH_LPSS_PWM_BAR_MS
BIT0
// Message Space
266
#define B_PCH_LPSS_PWM_BAR1_MS
BIT0
// Message Space
294
#define B_PCH_LPSS_PWM_PCS_PS (BIT1 |
BIT0
) // Power State
[
all
...]
PchRegsHda.h
52
#define B_PCH_HDA_PCS_PS (BIT1 |
BIT0
) // Power State - D0/D3 Hot
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
Lan9118DxeUtil.h
104
#define SOFT_RESET_CHECK_MAC_ADDR_LOAD
BIT0
116
#define PHY_RESET_PMT
BIT0
128
#define HW_CONF_USE_LEDS
BIT0
148
#define AUTO_NEGOTIATE_COLLISION_TEST
BIT0
166
#define STOP_TX_MAC
BIT0
178
#define STOP_RX_CLEAR
BIT0
188
#define START_TX_MAC
BIT0
200
#define START_RX_CLEAR
BIT0
239
#define ALLOC_USE_DEFAULT
BIT0
/device/linaro/bootloader/edk2/OvmfPkg/Include/
OvmfPlatforms.h
33
#define PMBA_RTE
BIT0
/device/linaro/bootloader/edk2/OvmfPkg/PlatformDxe/
PlatformConfig.h
56
#define PLATFORM_CONFIG_F_GRAPHICS_RESOLUTION
BIT0
/device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
Fdc.h
34
#define SELECT_DRV
BIT0
// Select Drive: 0=A 1=B
42
#define MSR_DAB
BIT0
// Drive A Busy
51
#define CCR_DRC (
BIT0
| BIT1) // Data Rate select
106
#define STS0_US0
BIT0
// Unit Select0
121
#define STS1_MA
BIT0
// Missing Address Mark
136
#define STS2_MD
BIT0
// Missing Address Mark in DataField
156
#define STS3_US0
BIT0
// Unit Select0
/device/linaro/bootloader/edk2/IntelFspPkg/Library/BaseCacheLib/
CacheLibInternal.h
36
#define B_EFI_MSR_CACHE_MEMORY_TYPE (BIT2 | BIT1 |
BIT0
)
53
#define B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 |
BIT0
)
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/
ExI.c
99
MmioOr32 ((UINTN) (GetPmcBase() + R_PCH_PMC_MTPMC1), (UINT32)
BIT0
+BIT1+BIT2);
101
MmioAnd32 ((UINTN) (GetPmcBase() + R_PCH_PMC_MTPMC1), ~((UINT32)
BIT0
+BIT1+BIT2)); //clear bit 0,1,2
/device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/
HdLcd.h
53
#define HDLCD_DMA_END
BIT0
/* DMA has finished reading a frame */
60
#define HDLCD_ENABLE
BIT0
63
#define HDLCD_BURST_1
BIT0
70
#define HDLCD_VSYNC_HIGH
BIT0
/device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/
IScsiBootFirmwareTable.h
86
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_FLAG_BOOT_FAILOVER
BIT0
103
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID
BIT0
127
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BLOCK_VALID
BIT0
155
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BLOCK_VALID
BIT0
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/
TPS65950.h
40
#define CARD_DETECT_ENABLE (BIT2 |
BIT0
) // GPIO ON + GPIO CD1 enabled
44
#define CARD_DETECT_BIT
BIT0
48
#define LEDAON
BIT0
Completed in 3421 milliseconds
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