| /device/linaro/bootloader/edk2/OptionRomPkg/AtapiPassThruDxe/ |
| AtapiPassThru.h | 73 #define IDE_PRIMARY_OPERATING_MODE BIT0
216 #define AMNF_ERR BIT0 ///< Address Mark Not Found
223 #define ILI_ERR BIT0 ///< Illegal Length Indication
233 #define HS0 BIT0
250 #define ERR BIT0 ///< Error
251 #define CHECK BIT0 ///< Check bit for ATAPI Status Reg
263 #define DMA BIT0
270 #define CoD BIT0
[all...] |
| /device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/ |
| PeCoffExtraActionLib.c | 36 return (BOOLEAN) (((Dr7 >> (RegisterIndex * 2)) & (BIT0 | BIT1)) == (BIT0 | BIT1));
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
| PchRegs.h | 45 #ifndef BIT0
46 #define BIT0 0x0001
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/VlvPlatformInitDxe/ |
| IgdOpRegion.h | 71 #define HD_MBOX1 BIT0
94 #define ALS_ENABLE BIT0
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/ |
| Omap3530I2c.h | 42 #define STT BIT0
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/ |
| XPressRich3.h | 47 #define PCIE_BAR_WIN_SUPPORT_IO BIT0
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Include/Protocol/ |
| FormBrowserEx.h | 37 #define BROWSER_ACTION_DISCARD BIT0
|
| VarCheck.h | 56 #define VAR_CHECK_VARIABLE_PROPERTY_READ_ONLY BIT0
|
| /device/linaro/bootloader/edk2/MdePkg/Include/Guid/ |
| Cper.h | 39 #define EFI_ERROR_RECORD_HEADER_PLATFORM_ID_VALID BIT0
48 #define EFI_ERROR_TIME_STAMP_PRECISE BIT0
143 #define EFI_ERROR_SECTION_FRU_ID_VALID BIT0
150 #define EFI_ERROR_SECTION_FLAGS_PRIMARY BIT0
226 #define EFI_GENERIC_ERROR_PROC_TYPE_VALID BIT0
280 #define EFI_GENERIC_ERROR_PROC_FLAGS_RESTARTABLE BIT0
340 #define EFI_CACHE_CHECK_TRANSACTION_TYPE_VALID BIT0
393 #define EFI_TLB_CHECK_TRANSACTION_TYPE_VALID BIT0
444 #define EFI_BUS_CHECK_TRANSACTION_TYPE_VALID BIT0
519 #define EFI_MS_CHECK_ERROR_TYPE_VALID BIT0
[all...] |
| /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
| Omap3530I2c.h | 42 #define STT BIT0
|
| /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/ |
| VirtioBlk.h | 50 #define VIRTIO_BLK_F_BARRIER BIT0
|
| VirtioScsi.h | 45 #define VIRTIO_SCSI_F_INOUT BIT0
|
| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Library/PlatformSecureLib/ |
| PlatformSecureLib.c | 83 return ((Buffer[1] & BIT0) != 0);
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/ |
| Ioh.h | 18 #ifndef BIT0
19 #define BIT0 0x01
136 #define B_IOH_USB_COMMAND_ISE BIT0
205 #define B_IOH_MAC_COMMAND_ISE BIT0
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/ |
| BoardClkGens.h | 66 #define CK410_GENERATOR_SPREAD_SPECTRUM_BIT BIT0
68 #define CK410_GENERATOR_CLOCK_FREERUN_BIT (BIT0 | BIT1 | BIT2)
76 #define CK505_GENERATOR_SPREAD_SPECTRUM_BIT (BIT0 | BIT1)
88 #define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BIT BIT0
|
| /device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/ |
| Acpi51.h | 196 #define EFI_ACPI_5_1_LEGACY_DEVICES BIT0
207 #define EFI_ACPI_5_1_ARM_PSCI_COMPLIANT BIT0
214 #define EFI_ACPI_5_1_WBINVD BIT0
263 #define EFI_ACPI_5_1_S4BIOS_F BIT0
270 #define EFI_ACPI_5_1_OSPM_64BIT_WAKE_F BIT0
301 #define EFI_ACPI_5_1_PCAT_COMPAT BIT0
342 #define EFI_ACPI_5_1_LOCAL_APIC_ENABLED BIT0
469 #define EFI_ACPI_5_1_CPEI_PROCESSOR_OVERRIDE BIT0
519 #define EFI_ACPI_5_1_GIC_ENABLED BIT0
562 #define EFI_ACPI_5_1_SPI_COUNT_BASE_SELECT BIT0
[all...] |
| Acpi60.h | 196 #define EFI_ACPI_6_0_LEGACY_DEVICES BIT0
207 #define EFI_ACPI_6_0_ARM_PSCI_COMPLIANT BIT0
214 #define EFI_ACPI_6_0_WBINVD BIT0
263 #define EFI_ACPI_6_0_S4BIOS_F BIT0
270 #define EFI_ACPI_6_0_OSPM_64BIT_WAKE_F BIT0
301 #define EFI_ACPI_6_0_PCAT_COMPAT BIT0
343 #define EFI_ACPI_6_0_LOCAL_APIC_ENABLED BIT0
470 #define EFI_ACPI_6_0_CPEI_PROCESSOR_OVERRIDE BIT0
522 #define EFI_ACPI_6_0_GIC_ENABLED BIT0
565 #define EFI_ACPI_6_0_SPI_COUNT_BASE_SELECT BIT0
[all...] |
| Acpi10.h | 473 #define EFI_ACPI_1_0_WBINVD BIT0
501 #define EFI_ACPI_1_0_S4BIOS_F BIT0
522 #define EFI_ACPI_1_0_PCAT_COMPAT BIT0
553 #define EFI_ACPI_1_0_LOCAL_APIC_ENABLED BIT0
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Library/BaseSerialPortLib16550/ |
| BaseSerialPortLib16550.c | 38 #define B_UART_FCR_FIFOE BIT0
43 #define B_UART_MCR_DTRC BIT0
46 #define B_UART_LSR_RXRDY BIT0
310 if (PcdGetBool (PcdSerialUseMmio) && ((SerialRegisterBase & BIT0) == 0)) {
318 if ((!PcdGetBool (PcdSerialUseMmio)) && ((SerialRegisterBase & BIT0) != 0)) {
368 if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister) & (BIT0 | BIT1)) != 0x00) {
369 PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1));
404 if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister) & (BIT0 | BIT1)) != 0x00) {
405 PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1));
[all...] |
| /device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/ |
| DebugCommunicationLibUsb3Transfer.c | 46 if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
55 ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
59 TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;
269 TRBPtr->CycleBit = (TRBPtr->CycleBit & BIT0) ? 0 : 1;
398 Trb->CycleBit = ((~Ring->RingPCS) & BIT0);
448 Trb->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| meminit.c | 165 isbM32m(MCU, PMSTS, BIT0, BIT0);
501 uint8_t speed = mrc_params->ddr_speed & (BIT1|BIT0); // For DDR3 --> 0 == 800, 1 == 1066, 2 == 1333
524 isbM32m(DDRPHY, (CMDPTRREG + (channel_i * DDRIOCCC_CH_OFFSET)), ~BIT0, BIT0); // WRPTRENABLE=0
529 isbM32m(DDRPHY, MASTERRSTN, 0, BIT0); // PHYRSTN=0
558 isbM32m(DDRPHY, (B01LATCTL1 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // Launch Time: ODT, DIFFAMP, ODT, DIFFAMP
578 isbM32m(DDRPHY, (B0LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
579 isbM32m(DDRPHY, (B1LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
582 isbM32m(DDRPHY, (B0RXIOBUFCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), ((0x0<<7)|(0x0<<0)), (BIT7|BIT0)); // AFE Bypass, RCVEN DIFFAMP
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/ |
| LcdGraphicsOutputDxe.h | 144 #define LCDENABLE BIT0
150 #define GFXENABLE BIT0
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/LcdGraphicsOutputDxe/ |
| LcdGraphicsOutputDxe.h | 144 #define LCDENABLE BIT0
150 #define GFXENABLE BIT0
|
| /system/bt/embdrv/sbc/decoder/include/ |
| oi_stddefs.h | 221 #ifndef BIT0
223 #define BIT0 \
320 #endif /* BIT0 et al */
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Flash/ |
| Flash.h | 77 #define NAND_FAILURE BIT0
|
