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  /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/
Omap3530MMCHS.h 23 #define SOFTRESET BIT1
36 #define INIT BIT1
58 #define BCE_ENABLE BIT1
82 #define DATI_MASK BIT1
84 #define DATI_NOT_ALLOWED BIT1
88 #define DTW_4_BIT BIT1
98 #define ICS_MASK BIT1
99 #define ICS BIT1
113 #define TC BIT1
124 #define TC_EN BIT1
    [all...]
  /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530MMCHS.h 23 #define SOFTRESET BIT1
36 #define INIT BIT1
58 #define BCE_ENABLE BIT1
82 #define DATI_MASK BIT1
84 #define DATI_NOT_ALLOWED BIT1
88 #define DTW_4_BIT BIT1
98 #define ICS_MASK BIT1
99 #define ICS BIT1
113 #define TC BIT1
124 #define TC_EN BIT1
    [all...]
  /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
PchRegsSata.h 76 #define B_PCH_SATA_COMMAND_MSE BIT1 // Memory Space Enable
95 #define B_PCH_SATA_PI_REGISTER_PNC BIT1 // Primary Mode Native Capable
145 #define B_PCH_SATA_ABAR_TP (BIT2 | BIT1) // Type
165 #define B_PCH_SATA_PMCS_PS (BIT1 | BIT0) // Power State
198 #define B_PCH_SATA_PCS_PORT1_EN BIT1 // Port 1 Enabled
207 #define B_PCH_SATA_PORT1_IMPLEMENTED BIT1 // Port 1 Implemented
PchRegsSpi.h 56 #define B_PCH_SPI_HSFS_FCERR BIT1 // Flash Cycle Error
83 #define B_PCH_SPI_OPTYPE0_MASK (BIT1 | BIT0) // Opcode Type 0 Mask
114 #define B_PCH_SPI_BCR_BLE BIT1 // Lock Enable (LE)
  /device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/
HdLcd.h 54 #define HDLCD_BUS_ERROR BIT1 /* DMA bus error */
64 #define HDLCD_BURST_2 BIT1
71 #define HDLCD_HSYNC_HIGH BIT1
SP804Timer.h 34 #define SP804_TIMER_CTRL_32BIT BIT1
  /device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/
IScsiBootFirmwareTable.h 104 #define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED BIT1
128 #define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BOOT_SELECTED BIT1
156 #define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BOOT_SELECTED BIT1
  /device/linaro/bootloader/edk2/DuetPkg/PciBusNoEnumerationDxe/
PciPowerManagement.c 86 PowerManagementCSR &= ~(BIT8 | BIT1 | BIT0);
  /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/
Isp1761UsbDxe.h 43 #define ISP1761_DC_INTERRUPT_SOF BIT1
83 #define ISP1761_CTRL_FUNCTION_STATUS BIT1
99 #define ISP1761_OTG_CTRL_DP_PULLDOWN BIT1
104 #define ISP1761_OTG_STATUS_A_B_SESS_VLD BIT1
  /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/PciBusDxe/
PciPowerManagement.c 73 PowerManagementCSR &= ~(BIT8 | BIT1 | BIT0);
  /device/linaro/bootloader/edk2/SecurityPkg/Include/Guid/
TrEEPhysicalPresenceData.h 38 #define TREE_FLAG_NO_PPI_CLEAR BIT1
PhysicalPresenceData.h 74 #define FLAG_NO_PPI_CLEAR BIT1
  /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibDxe/
I2CRegs.h 64 #define I2C_INTR_RX_OVER BIT1
89 #define STAT_TFNF BIT1 // TX FIFO is not full
124 #define I2C_INTR_RX_OVER BIT1
128 #define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
  /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibPei/
I2CAccess.h 28 #define B_PCH_LPC_ACPI_BASE_EN BIT1 // Enable Bit
I2CLibPei.h 31 #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC1 BIT1 // LPSS I2C #1 Disable
45 #define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable
51 #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type
58 #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type
67 #define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
117 #define I2C_INTR_RX_OVER BIT1
142 #define STAT_TFNF BIT1 // TX FIFO is not full
181 #define I2C_INTR_RX_OVER BIT1
  /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/
IdeMode.h 66 #define BMIS_ERROR BIT1
119 #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR BIT1
  /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
VirtioNet.h 45 #define VIRTIO_NET_F_GUEST_CSUM BIT1 // guest to checksum incoming packets
95 #define VIRTIO_NET_S_ANNOUNCE BIT1
  /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/
Lan91xDxeHw.h 76 #define TCR_LOOP BIT1
91 #define EPHSR_SNGLCOL BIT1
106 #define RCR_PRMS BIT1
138 #define CTR_RELOAD BIT1
184 #define IST_TX BIT1
193 #define MGMT_MDI BIT1
256 #define PHYSTS_JABBER BIT1 // Jabber condition detected
  /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
Lan9118DxeHw.h 62 #define RXSTATUS_CRC_ERROR BIT1 // Cyclic Redundancy Check Error
130 #define HWCFG_SRST_TO BIT1 // Software Reset Timeout bit (RO)
137 #define MPTCTRL_PME_EN BIT1 // Enable external PME signals
159 #define PHYSTS_JABBER BIT1 // Jabber condition detected
220 #define WUCSR_MPEN BIT1 // Magic Packet enable (allow wake from Magic P)
235 #define TXCFG_TX_ON BIT1 // Start the transmitter
265 #define MII_ACC_MII_WRITE BIT1
  /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/
IdeData.h 114 #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR BIT1
125 #define BMIS_ERROR BIT1
304 #define IE0 BIT1
  /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/
PL180Mci.h 73 #define MCI_POWER_UP BIT1
74 #define MCI_POWER_ON (BIT1 | BIT0)
84 #define MCI_STATUS_CMD_DATACRCFAIL BIT1
134 #define MCI_DATACTL_CARD_TO_CONT BIT1
  /device/linaro/bootloader/edk2/OvmfPkg/AcpiTables/
Platform.h 60 #define RESET_VALUE (BIT2 | BIT1) // PIIX3 Reset CPU + System Reset
  /device/linaro/bootloader/edk2/OvmfPkg/Library/ResetSystemLib/
ResetSystemLib.c 50 IoWrite8 (0xCF9, BIT2 | BIT1); // 1st choice: PIIX3 RCR, RCPU|SRST
  /device/linaro/bootloader/edk2/QuarkPlatformPkg/Library/PlatformBootManagerLib/
PlatformBootManager.h 47 #define CONSOLE_IN BIT1
  /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/
QuarkNcSocId.h 239 #define SMM_READ_OPEN (BIT1) // SMM Reads OPEN
330 #define B_CFG_STICKY_RW_HMB_VIOLATION BIT1
397 #define B_QNC_SMBUS_DERR (BIT1) // Device Error
497 #define B_QNC_GPE0BLK_SMIE_SWT (BIT1) // Software Timer
512 #define B_QNC_GPE0BLK_SMIS_SWT (BIT1) // Software Timer
545 #define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0)
568 #define B_QNC_LPC_BIOS_CNTL_BLE (BIT1)
616 #define B_RST_CNT_WARM_RST (BIT1) // Warm reset
654 #define B_QNC_PCIE_DCTL_NFE (BIT1) //Non Fatal error Reporting Enable
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