| /prebuilts/ndk/r11/platforms/android-23/arch-arm/usr/include/linux/ |
| synclink.h | 52 #define BIT23 0x00800000
|
| /prebuilts/ndk/r11/platforms/android-23/arch-arm64/usr/include/linux/ |
| synclink.h | 52 #define BIT23 0x00800000
|
| /prebuilts/ndk/r11/platforms/android-23/arch-mips/usr/include/linux/ |
| synclink.h | 52 #define BIT23 0x00800000
|
| /prebuilts/ndk/r11/platforms/android-23/arch-mips64/usr/include/linux/ |
| synclink.h | 52 #define BIT23 0x00800000
|
| /prebuilts/ndk/r11/platforms/android-23/arch-x86/usr/include/linux/ |
| synclink.h | 52 #define BIT23 0x00800000
|
| /prebuilts/ndk/r11/platforms/android-23/arch-x86_64/usr/include/linux/ |
| synclink.h | 52 #define BIT23 0x00800000
|
| /prebuilts/ndk/r11/platforms/android-24/arch-arm/usr/include/linux/ |
| synclink.h | 52 #define BIT23 0x00800000
|
| /prebuilts/ndk/r11/platforms/android-24/arch-arm64/usr/include/linux/ |
| synclink.h | 52 #define BIT23 0x00800000
|
| /prebuilts/ndk/r11/platforms/android-24/arch-mips/usr/include/linux/ |
| synclink.h | 52 #define BIT23 0x00800000
|
| /prebuilts/ndk/r11/platforms/android-24/arch-mips64/usr/include/linux/ |
| synclink.h | 52 #define BIT23 0x00800000
|
| /prebuilts/ndk/r11/platforms/android-24/arch-x86/usr/include/linux/ |
| synclink.h | 52 #define BIT23 0x00800000
|
| /prebuilts/ndk/r11/platforms/android-24/arch-x86_64/usr/include/linux/ |
| synclink.h | 52 #define BIT23 0x00800000
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/ |
| VlvCommonDefinitions.h | 100 #define BIT23 0x00800000
|
| /device/linaro/bootloader/edk2/MdePkg/Include/ |
| Base.h | 249 #define BIT23 0x00800000
[all...] |
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/ |
| QNCCommonDefinitions.h | 93 #define BIT23 0x00800000
|
| QuarkNcSocId.h | 342 #define B_MUXTOP_FLEX2_MASK (BIT25 | BIT24 | BIT23)
[all...] |
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/ |
| IohCommonDefinitions.h | 93 #define BIT23 0x00800000
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
| XhcPeim.c | [all...] |
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| meminit.c | 594 isbM32m(DDRPHY, (CMDOBSCKEBBCTL + (channel_i * DDRIOCCC_CH_OFFSET)), 0, (BIT23));
603 isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: SFR (regulator), MPLL
604 isbM32m(DDRPHY, (CMDPMDLYREG3 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFU<<28)|(0xFFF<<16)|(0xF<<12)|(0x616<<0)), ((BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12)|(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT_for_PM_MSG_gt0, MDLL Turn On
605 isbM32m(DDRPHY, (CMDPMDLYREG2 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // MPLL Divider Reset Delays
606 isbM32m(DDRPHY, (CMDPMDLYREG1 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn Off Delays: VREG, Staggered MDLL, MDLL, PI
607 isbM32m(DDRPHY, (CMDPMDLYREG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: MPLL, Staggered MDLL, PI, IOBUFACT
608 isbM32m(DDRPHY, (CMDPMCONFIG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0x6<<8)|BIT6|(0x4<<0)), (BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|(BIT11|BIT10|BIT9|BIT8)|BIT6|(BIT3|BIT2|BIT1|BIT0))); // Allow PUnit signals
[all...] |
| meminit_utils.c | 61 msk = (byte_lane & BIT0) ? (BIT23 | BIT22 | BIT21 | BIT20) : (BIT11 | BIT10 | BIT9 | BIT8);
[all...] |
| /external/syslinux/gpxe/src/drivers/net/ |
| wlan_compat.h | 219 #define BIT23 0x00800000
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
| Xhci.c | 517 State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
634 State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
[all...] |
| /device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/ |
| Tpm12.h | [all...] |
