| /device/linaro/bootloader/edk2/MdePkg/Library/BasePrintLib/ |
| PrintLibInternal.h | 32 #define PAD_TO_WIDTH BIT9
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| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| PchRegsSpi.h | 79 #define B_PCH_SPI_OPTYPE4_MASK (BIT9 | BIT8) // Opcode Type 4 Mask
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| PchRegsSmbus.h | 55 #define B_PCH_SMBUS_PCICMD_FBE BIT9 // FBE - reserved as '0'
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| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/ |
| CommonIncludes.h | 107 #define BIT9 0x00000200
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| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
| XhciReg.h | 152 #define XHC_USBSTS_RSS BIT9 // Restore State Status
171 #define XHC_PORTSC_PP BIT9 // Port Power
187 #define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
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| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
| XhciReg.h | 67 #define XHC_USBSTS_RSS BIT9 // Restore State Status
86 #define XHC_PORTSC_PP BIT9 // Port Power
102 #define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
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| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibPei/ |
| I2CLibPei.h | 96 #define B_CMD_STOP BIT9 // 1 = STOP
111 #define I2C_INTR_STOP_DET BIT9
175 #define I2C_INTR_STOP_DET BIT9
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| /device/linaro/bootloader/edk2/IntelFspPkg/FspSecCore/Ia32/ |
| InitializeFpu.s | 61 orl $BIT9, %eax
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| InitializeFpu.asm | 64 or eax, BIT9
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| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
| PchRegs.h | 55 #define BIT9 0x0200
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| /device/linaro/bootloader/edk2/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/ |
| InitializeFpu.asm | 64 or eax, BIT9
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| /device/linaro/bootloader/edk2/UefiCpuPkg/Library/BaseUefiCpuLib/X64/ |
| InitializeFpu.asm | 54 or rax, BIT9
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| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
| BoardFeatures.h | 56 #define B_BOARD_FEATURES_MINI_CARD BIT9
150 #define B_BOARD_FEATURES_ECIR BIT9 // Enhanced Consumer IR
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| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| meminit.c | 558 isbM32m(DDRPHY, (B01LATCTL1 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // Launch Time: ODT, DIFFAMP, ODT, DIFFAMP
566 isbM32m(DDRPHY, (B0ONDURCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT13|BIT12|BIT11|BIT10|BIT9|BIT8))); // On Duration: ODT, DIFFAMP
567 isbM32m(DDRPHY, (B1ONDURCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT13|BIT12|BIT11|BIT10|BIT9|BIT8))); // On Duration: ODT, DIFFAMP
578 isbM32m(DDRPHY, (B0LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
579 isbM32m(DDRPHY, (B1LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
600 isbM32m(DDRPHY, (CMDRCOMPODT + (channel_i * DDRIOCCC_CH_OFFSET)), ((0x03<<5)|(0x03<<0)), ((BIT9|BIT8|BIT7|BIT6|BIT5)|(BIT4|BIT3|BIT2|BIT1|BIT0)));
603 isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: SFR (regulator), MPLL
604 isbM32m(DDRPHY, (CMDPMDLYREG3 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFU<<28)|(0xFFF<<16)|(0xF<<12)|(0x616<<0)), ((BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12)|(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT_for_PM_MSG_gt0, MDLL Turn On
605 isbM32m(DDRPHY, (CMDPMDLYREG2 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // MPLL Divider Reset Delays
606 isbM32m(DDRPHY, (CMDPMDLYREG1 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn Off Delays: VREG, Staggered MDLL, MDLL, (…)
[all...] |
| meminit_utils.c | 61 msk = (byte_lane & BIT0) ? (BIT23 | BIT22 | BIT21 | BIT20) : (BIT11 | BIT10 | BIT9 | BIT8);
361 msk = (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8);
378 msk |= (byte_lane & BIT0) ? (BIT9) : (BIT6);
453 msk = (BIT11 | BIT10 | BIT9 | BIT8);
473 | (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) | (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
570 msk = (BIT15 | BIT14 | BIT13 | BIT12) | (BIT11 | BIT10 | BIT9 | BIT8);
582 msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16) | (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8);
608 msk |= (BIT11 | BIT10 | BIT9 | BIT8); // only ??? matters
1078 msk[0] = (rcvn) ? (BIT1) : (BIT9); // BL0
[all...] |
| gen5_iosf_sb_definitions.h | 437 #define DDR3_EMRS2_RTTWR_60 (BIT9)
444 #define DDR3_EMRS1_RTTNOM_20 (BIT9)
445 #define DDR3_EMRS1_RTTNOM_30 (BIT9|BIT2)
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| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/ |
| LcdGraphicsOutputDxe.h | 147 #define DATALINES24 (BIT8 | BIT9)
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| /device/linaro/bootloader/edk2/ArmPkg/Include/Chipset/ |
| AArch64Mmu.h | 40 ((UINTN)(TranslationTable) + ((((UINTN)(Address) >> TT_ADDRESS_OFFSET_AT_LEVEL(Level)) & (BIT9-1)) * sizeof(UINT64)))
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| /device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/ |
| BaseTypes.h | 230 #define BIT9 0x00000200
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| /device/linaro/bootloader/edk2/Omap35xxPkg/LcdGraphicsOutputDxe/ |
| LcdGraphicsOutputDxe.h | 147 #define DATALINES24 (BIT8 | BIT9)
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| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/ |
| QuarkNcSocId.h | 291 #define B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK (BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
309 #define B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK (BIT9 | BIT8)
334 #define B_CFG_STICKY_RW_FORCE_RECOVERY BIT9
649 #define B_QNC_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) // L1 Acceptable exit latency
[all...] |
| /system/bt/embdrv/sbc/decoder/include/ |
| oi_stddefs.h | 250 #define BIT9 \
|
| /device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/ |
| Pci22.h | 590 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200
604 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200
613 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200
|
| PeImage.h | 105 #define EFI_IMAGE_FILE_DEBUG_STRIPPED BIT9 ///< 0x0200 Debugging info stripped from file in .DBG file.
309 #define EFI_IMAGE_SCN_LNK_INFO BIT9 ///< 0x00000200 ///< Section contains comments or some other type of information.
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| /external/syslinux/gpxe/src/include/gpxe/efi/IndustryStandard/ |
| Pci22.h | 390 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200
404 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200
413 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200
|
