| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/ |
| attr-gnu-4-75.d | 8 Tag_GNU_MIPS_ABI_FP: Hard float compat \(32-bit CPU, 64-bit FPU\)
16 FP ABI: Hard float compat \(32-bit CPU, 64-bit FPU\)
|
| attr-gnu-4-76.d | 8 Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\)
16 FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
|
| attr-gnu-4-77.d | 8 Tag_GNU_MIPS_ABI_FP: Hard float compat \(32-bit CPU, 64-bit FPU\)
16 FP ABI: Hard float compat \(32-bit CPU, 64-bit FPU\)
|
| attr-gnu-4-4-ph.d | 19 FP ABI: Hard float \(MIPS32r2 64-bit FPU 12 callee-saved\)
|
| attr-gnu-4-5-ph.d | 19 FP ABI: Hard float \(32-bit CPU, Any FPU\)
|
| attr-gnu-4-6-ph.d | 19 FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
|
| attr-gnu-4-7-ph.d | 19 FP ABI: Hard float compat \(32-bit CPU, 64-bit FPU\)
|
| abiflags-strip10-ph.d | 21 FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
|
| abiflags-strip2-ph.d | 21 FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
|
| abiflags-strip3-ph.d | 21 FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
|
| abiflags-strip8-ph.d | 21 FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
|
| abiflags-strip9-ph.d | 21 FP ABI: Hard float compat \(32-bit CPU, 64-bit FPU\)
|
| abiflags-strip4-ph.d | 23 FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
|
| abiflags-strip5-ph.d | 23 FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
|
| /external/llvm/test/MC/ARM/ |
| directive-fpu-diagnostics.s | 7 .fpu invalid
8 @ CHECK: error: Unknown FPU name
9 @ CHECK: .fpu invalid
|
| directive-fpu-softvfp.s | 3 @ Check softvfp as the FPU name.
8 .fpu softvfp
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips32r2-ill-fp64.s | 49 # Even registers are supported w/ 32-bit FPU, odd
50 # registers supported only for 64-bit FPU.
51 # This file tests 64-bit FPU.
|
| mips32r2-ill.s | 49 # Even registers are supported w/ 32-bit FPU, odd
50 # registers supported only for 64-bit FPU.
51 # This file tests 32-bit FPU.
|
| mipsr6@mips32r2-ill.s | 49 # Even registers are supported w/ 32-bit FPU, odd
50 # registers supported only for 64-bit FPU.
51 # This file tests 32-bit FPU.
|
| elf_arch_mips32r6.d | 15 FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
|
| elf_arch_mips64r6.d | 15 FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
|
| /external/llvm/test/MC/Mips/ |
| nooddspreg-error.s | 9 # CHECK-ERROR: :[[@LINE-1]]:15: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-ERROR: :[[@LINE-2]]:25: error: -mno-odd-spreg prohibits the use of odd FPU registers
|
| /external/swiftshader/third_party/LLVM/test/MC/MBlaze/ |
| mblaze_pattern.s | 3 # Test to ensure that all FPU instructions can be parsed by the
|
| /device/linaro/bootloader/edk2/StdLib/LibC/Main/X64/ |
| fpu_rmode.asm | 2 ; Return the current FPU rounding mode.
34 fnstcw [rsp + 8] ; save 16-bit FPU Control Word
35 mov eax, [rsp + 8] ; get the saved FPU Control Word
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| nds32-asm.c | 520 {"flsi", "=fst,[%ra{+%i12s2}]", OP6 (LWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
521 {"flsi.bi", "=fst,[%ra],%i12s2", FPU_RA_IMMBI (LWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
523 {"fssi", "=fst,[%ra{+%i12s2}]", OP6 (SWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
524 {"fssi.bi", "=fst,[%ra],%i12s2", FPU_RA_IMMBI (SWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
526 {"fldi", "=fdt,[%ra{+%i12s2}]", OP6 (LDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
527 {"fldi.bi", "=fdt,[%ra],%i12s2", FPU_RA_IMMBI (LDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
529 {"fsdi", "=fdt,[%ra{+%i12s2}]", OP6 (SDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
530 {"fsdi.bi", "=fdt,[%ra],%i12s2", FPU_RA_IMMBI (SDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
533 {"fadds", "=fst,%fsa,%fsb", FS1 (FADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
534 {"fsubs", "=fst,%fsa,%fsb", FS1 (FSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}
[all...] |
