| /external/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
| Locked.cpp | 42 const uint32_t V0 = (Value0)&Mask##Size; \
50 test.setDwordTo(T0, V0); \
53 ASSERT_EQ(V0, test.Dst1()) << TestString; \
93 const uint32_t V0 = (Value0)&Mask##Size; \
105 ASSERT_EQ(V0, test.Reg1()) << TestString; \
151 const uint32_t V0 = (Value0)&Mask##Size; \
160 test.setDwordTo(T0, V0); \
163 ASSERT_EQ(V0, test.Dst1()) << TestString; \
164 ASSERT_EQ(Mask##Size &(V1 + V0), test.contentsOfDword(T0)) << TestString; \
295 static constexpr uint64_t V0 = ValueMem;
[all...] |
| /external/webp/src/dsp/ |
| yuv_sse2.c | 31 const __m128i* const V0,
47 const __m128i R0 = _mm_mulhi_epu16(*V0, k26149);
52 const __m128i G1 = _mm_mulhi_epu16(*V0, k13320);
87 const __m128i Y0 = Load_HI_16(y), U0 = Load_HI_16(u), V0 = Load_HI_16(v);
88 ConvertYUV444ToRGB(&Y0, &U0, &V0, R, G, B);
96 const __m128i Y0 = Load_HI_16(y), U0 = Load_UV_HI_8(u), V0 = Load_UV_HI_8(v);
97 ConvertYUV444ToRGB(&Y0, &U0, &V0, R, G, B);
652 __m128i rgb[6], U0, V0, U1, V1;
657 ConvertRGBToUV(&rgb[0], &rgb[2], &rgb[4], &U0, &V0);
666 V0 = _mm_packus_epi16(V0, V1)
838 const int v0 = (8 * A[i + 0] + 2 * a1b0 + a0a1b0b1) >> 4; local
[all...] |
| upsampling_neon.c | 144 const int16x8_t V0 = vreinterpretq_s16_u16(vshll_n_u8(v, 7)); \
146 const int16x8_t R0 = vqdmulhq_lane_s16(V0, coeff1, 1); \
148 const int16x8_t G1 = vqdmulhq_lane_s16(V0, coeff1, 3); \
219 const int v0 = (top_v[0] + v_diag) >> 1; \
220 VP8YuvTo ## FMT(top_y[0], u0, v0, top_dst); \
224 const int v0 = (cur_v[0] + v_diag) >> 1; \
225 VP8YuvTo ## FMT(bottom_y[0], u0, v0, bottom_dst); \
|
| /art/compiler/jni/quick/mips64/ |
| calling_convention_mips64.cc | 79 return Mips64ManagedRegister::FromGpuRegister(V0);
92 return Mips64ManagedRegister::FromGpuRegister(V0);
|
| /hardware/interfaces/tests/baz/1.0/ |
| IBase.hal | 68 V0 = 1 << 0,
|
| /libcore/luni/src/test/java/libcore/java/lang/ |
| ClassCastExceptionTest.java | 81 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
86 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
|
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/ |
| inst.go | 127 V0 // VSX extension, F0 is V0[0:63].
232 case V0 <= r && r <= V31:
233 return fmt.Sprintf("v%d", int(r-V0))
|
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/ |
| inst.go | 127 V0 // VSX extension, F0 is V0[0:63].
232 case V0 <= r && r <= V31:
233 return fmt.Sprintf("v%d", int(r-V0))
|
| /prebuilts/go/darwin-x86/src/math/big/ |
| arith_s390x.s | 98 VZERO V0 // c = 0
110 VACCCQ V1, V9, V0, V25
111 VACQ V1, V9, V0, V17
153 VACCCQ V8, V16, V31, V0 //V0 has carry-over
169 VLGVG $1, V0, R4 // put cf into R4
337 VZERO V0 // cf = 0
339 VLVGG $1, R4, V0 //put carry into V0
352 VSBCBIQ V1, V9, V0, V2
[all...] |
| /prebuilts/go/linux-x86/src/math/big/ |
| arith_s390x.s | 98 VZERO V0 // c = 0
110 VACCCQ V1, V9, V0, V25
111 VACQ V1, V9, V0, V17
153 VACCCQ V8, V16, V31, V0 //V0 has carry-over
169 VLGVG $1, V0, R4 // put cf into R4
337 VZERO V0 // cf = 0
339 VLVGG $1, R4, V0 //put carry into V0
352 VSBCBIQ V1, V9, V0, V2
[all...] |
| /art/runtime/arch/mips/ |
| registers_mips.h | 32 V0 = 2, // Values.
|
| /art/runtime/arch/mips64/ |
| registers_mips64.h | 32 V0 = 2, // Values.
|
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 76 unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
79 V0 = RegInfo.createVirtualRegister(RC);
83 BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0)
88 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
|
| MipsSEISelDAGToDAG.cpp | 141 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
146 V0 = RegInfo.createVirtualRegister(RC);
153 // lui $v0, %hi(%neg(%gp_rel(fname)))
154 // daddu $v1, $v0, $t9
157 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
159 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
169 // lui $v0, %hi(__gnu_local_gp)
170 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
171 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
173 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
[all...] |
| /hardware/interfaces/tests/foo/1.0/ |
| IFoo.hal | 37 V0 = 1 << 0,
41 VALL = V0 | V1 | V2 | V3,
|
| /external/llvm/unittests/Analysis/ |
| ScalarEvolutionTest.cpp | 59 Value *V0 = new GlobalVariable(M, Ty, false, GlobalValue::ExternalLinkage, Init, "V0");
65 const SCEV *S0 = SE.getSCEV(V0);
85 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0);
91 V1->replaceAllUsesWith(V0);
93 // After the RAUWs, these should all be pointing to V0.
94 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0);
95 EXPECT_EQ(cast<SCEVUnknown>(M1->getOperand(1))->getValue(), V0);
96 EXPECT_EQ(cast<SCEVUnknown>(M2->getOperand(1))->getValue(), V0);
|
| /external/swiftshader/third_party/LLVM/unittests/Analysis/ |
| ScalarEvolutionTest.cpp | 48 Value *V0 = new GlobalVariable(M, Ty, false, GlobalValue::ExternalLinkage, Init, "V0");
56 const SCEV *S0 = SE.getSCEV(V0);
76 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0);
82 V1->replaceAllUsesWith(V0);
84 // After the RAUWs, these should all be pointing to V0.
85 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0);
86 EXPECT_EQ(cast<SCEVUnknown>(M1->getOperand(1))->getValue(), V0);
87 EXPECT_EQ(cast<SCEVUnknown>(M2->getOperand(1))->getValue(), V0);
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 274 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
275 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
276 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
279 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
280 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
281 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| PPCBaseInfo.h | 31 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0;
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 257 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
258 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
259 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
260 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
263 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
264 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
265 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
[all...] |
| /art/compiler/jni/quick/mips/ |
| calling_convention_mips.cc | 94 return MipsManagedRegister::FromCoreRegister(V0);
107 return MipsManagedRegister::FromCoreRegister(V0);
|
| /external/clang/test/CodeGen/ |
| ext-vector.c | 282 int4 test15(uint4 V0) {
284 int4 V = !V0;
|
| /prebuilts/go/darwin-x86/src/go/internal/gcimporter/testdata/ |
| exports.go | 77 V0 int
|
| /prebuilts/go/linux-x86/src/go/internal/gcimporter/testdata/ |
| exports.go | 77 V0 int
|
| /art/compiler/utils/mips64/ |
| assembler_mips64_test.cc | 92 registers_.push_back(new mips64::GpuRegister(mips64::V0));
125 secondary_register_names_.emplace(mips64::GpuRegister(mips64::V0), "v0");
[all...] |
