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    Searched refs:getRegisterInfo (Results 201 - 225 of 424) sorted by null

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  /external/llvm/lib/CodeGen/AsmPrinter/
DwarfCompileUnit.cpp 307 const TargetRegisterInfo *RI = Asm->MF->getSubtarget().getRegisterInfo();
553 DwarfExpr.AddMachineRegIndirect(*Asm->MF->getSubtarget().getRegisterInfo(),
781 const TargetRegisterInfo &TRI = *Asm->MF->getSubtarget().getRegisterInfo();
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AsmPrinterInlineAsm.cpp 143 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
  /external/swiftshader/third_party/LLVM/lib/CodeGen/
RegAllocPBQP.cpp 200 const TargetRegisterInfo *tri = mf->getTarget().getRegisterInfo();
347 CoalescerPair cp(*tm.getInstrInfo(), *tm.getRegisterInfo());
643 tri = tm->getRegisterInfo();
  /external/swiftshader/third_party/LLVM/lib/CodeGen/AsmPrinter/
DwarfCompileUnit.cpp 212 const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo();
225 const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo();
227 const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo();
394 const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo();
    [all...]
  /external/llvm/lib/Target/ARM/
ARMAsmPrinter.cpp 187 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
265 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
297 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
353 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
379 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
394 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
    [all...]
ARMBaseInstrInfo.cpp 817 const TargetRegisterInfo *TRI = &getRegisterInfo();
919 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
936 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
    [all...]
ARMBaseInstrInfo.h 111 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
MLxExpansionPass.cpp 385 TRI = Fn.getSubtarget().getRegisterInfo();
  /external/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp     [all...]
  /external/llvm/lib/CodeGen/MIRParser/
MIParser.cpp 776 const auto *TRI = MF.getSubtarget().getRegisterInfo();
    [all...]
  /external/llvm/lib/Target/ARM/MCTargetDesc/
ARMELFStreamer.cpp     [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonVLIWPacketizer.cpp 110 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
178 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
406 if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo()))
    [all...]
  /external/llvm/include/llvm/MC/
MCContext.h 249 const MCRegisterInfo *getRegisterInfo() const { return MRI; }
  /external/llvm/lib/CodeGen/
LiveDebugValues.cpp 508 TRI = MF.getSubtarget().getRegisterInfo();
LiveRangeEdit.cpp 443 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
MachineCombiner.cpp 455 TRI = STI.getRegisterInfo();
RegisterScavenging.cpp 66 TRI = MF.getSubtarget().getRegisterInfo();
  /external/llvm/lib/Target/AArch64/
AArch64PBQPRegAlloc.cpp 331 TRI = MF.getSubtarget().getRegisterInfo();
AArch64TargetMachine.cpp 237 new AArch64RegisterBankInfo(*I->getRegisterInfo()));
  /external/llvm/lib/Target/AMDGPU/
AMDGPUISelDAGToDAG.cpp 204 return Subtarget->getRegisterInfo()->getRegClass(RegClass);
209 Subtarget->getRegisterInfo()->getRegClass(RCID);
213 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
290 const AMDGPURegisterInfo *TRI = Subtarget->getRegisterInfo();
    [all...]
R600Packetizer.cpp 154 TRI(TII->getRegisterInfo()) {
SIInsertWaits.cpp 519 TRI = &TII->getRegisterInfo();
SILoadStoreOptimizer.cpp 419 TRI = &TII->getRegisterInfo();
SIWholeQuadMode.cpp 469 TRI = &TII->getRegisterInfo();
  /external/llvm/lib/Target/AMDGPU/Disassembler/
AMDGPUDisassembler.cpp 164 return getContext().getRegisterInfo()->

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