| /external/llvm/lib/Target/Hexagon/ |
| HexagonGenMux.cpp | 315 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
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| HexagonNewValueJump.cpp | 404 MF.getSubtarget().getRegisterInfo());
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| HexagonStoreWidening.cpp | 603 TRI = ST.getRegisterInfo();
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| /external/llvm/lib/Target/Sparc/ |
| DelaySlotFiller.cpp | 349 for (MCRegAliasIterator AI(Reg, Subtarget->getRegisterInfo(), true);
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 504 TRI = &TII->getRegisterInfo();
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| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 178 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
182 const X86RegisterInfo &getRegisterInfo() const { return RI; }
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| X86SelectionDAGInfo.cpp | 39 DAG.getSubtarget().getRegisterInfo());
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| ExecutionDepsFix.cpp | 453 TRI = MF->getTarget().getRegisterInfo();
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| LLVMTargetMachine.cpp | 369 *getRegisterInfo(),
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| MachineInstr.cpp | 236 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
[all...] |
| MachineSink.cpp | 216 TRI = TM.getRegisterInfo();
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| ShrinkWrapping.cpp | 404 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
[all...] |
| IfConversion.cpp | 263 TRI = MF.getTarget().getRegisterInfo();
271 MF.getTarget().getRegisterInfo(),
405 MF.getTarget().getRegisterInfo(),
[all...] |
| /external/swiftshader/third_party/LLVM/lib/MC/MCParser/ |
| COFFAsmParser.cpp | 438 const MCRegisterInfo &MRI = getContext().getRegisterInfo();
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| /external/llvm/lib/Target/AArch64/ |
| AArch64CollectLOH.cpp | 293 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
[all...] |
| AArch64ExpandPseudoInsts.cpp | 609 LivePhysRegs LiveRegs(&TII->getRegisterInfo());
687 LivePhysRegs LiveRegs(&TII->getRegisterInfo());
[all...] |
| AArch64InstrInfo.cpp | 659 const TargetRegisterInfo *TRI = &getRegisterInfo();
753 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCCodeEmitter.cpp | 130 MCT.getRegisterInfo()->getEncodingValue(HMB.getOperand(i).getReg());
808 return MCT.getRegisterInfo()->getEncodingValue(Reg);
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| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.cpp | 254 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
301 const TargetRegisterInfo &RI = *MF->getSubtarget().getRegisterInfo();
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 58 computeRegisterProperties(Subtarget->getRegisterInfo());
603 Subtarget->getRegisterInfo()->getFrameRegister(DAG.getMachineFunction());
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| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 228 const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo();
265 MIB->addRegisterKilled(XCore::LR, MF.getSubtarget().getRegisterInfo(),
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 113 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
666 const TargetRegisterInfo *TRI = &getRegisterInfo();
742 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
758 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
891 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
[all...] |
| /external/llvm/lib/CodeGen/ |
| IfConversion.cpp | 292 TRI = ST.getRegisterInfo();
306 BFChange = BF.OptimizeFunction(MF, TII, ST.getRegisterInfo(),
430 BF.OptimizeFunction(MF, TII, MF.getSubtarget().getRegisterInfo(),
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineRegisterInfo.h | 131 return MF->getSubtarget().getRegisterInfo();
[all...] |
