| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-3957855/prebuilt_include/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-3960126/prebuilt_include/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-3977809/prebuilt_include/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 319 unsigned getSubReg() const {
851 SR = Start->getSubReg();
854 SR = End->getSubReg();
869 DistSR = End->getSubReg();
880 SubIB.addReg(End->getReg(), 0, End->getSubReg())
881 .addReg(Start->getReg(), 0, Start->getSubReg());
884 .addReg(Start->getReg(), 0, Start->getSubReg());
898 SubIB.addReg(End->getReg(), 0, End->getSubReg())
[all...] |
| HexagonEarlyIfConv.cpp | 440 if (RO1.getSubReg() != 0 || RO3.getSubReg() != 0) {
785 SR = RO.getReg(), SSR = RO.getSubReg();
787 TR = RO.getReg(), TSR = RO.getSubReg();
789 FR = RO.getReg(), FSR = RO.getSubReg();
[all...] |
| HexagonFrameLowering.cpp | 826 unsigned HiReg = HRI.getSubReg(Reg, Hexagon::subreg_hireg);
827 unsigned LoReg = HRI.getSubReg(Reg, Hexagon::subreg_loreg);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| MachineInstr.cpp | 120 if (SubIdx && getSubReg())
121 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
129 if (getSubReg()) {
130 Reg = TRI.getSubReg(Reg, getSubReg());
131 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
197 getSubReg() == Other.getSubReg();
240 OS << PrintReg(getReg(), TRI, getSubReg());
[all...] |
| VirtRegRewriter.cpp | 70 if (MO.getSubReg()) {
710 if (TRI->getSubReg(Reg, SubIdx) == SubReg)
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 343 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
493 unsigned getSubReg() const {
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| TargetRegisterInfo.h | 370 /// getSubReg - Returns the physical register number of sub-register "Index"
373 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
385 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
|
| /prebuilts/clang/host/darwin-x86/clang-3957855/prebuilt_include/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 353 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
507 unsigned getSubReg() const {
|
| /prebuilts/clang/host/darwin-x86/clang-3960126/prebuilt_include/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 353 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
507 unsigned getSubReg() const {
|
| /prebuilts/clang/host/darwin-x86/clang-3977809/prebuilt_include/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 353 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
507 unsigned getSubReg() const {
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 353 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
507 unsigned getSubReg() const {
|
| /prebuilts/clang/host/linux-x86/clang-3957855/prebuilt_include/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 353 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
507 unsigned getSubReg() const {
|
| /prebuilts/clang/host/linux-x86/clang-3960126/prebuilt_include/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 353 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
507 unsigned getSubReg() const {
|
| /prebuilts/clang/host/linux-x86/clang-3977809/prebuilt_include/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 353 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
507 unsigned getSubReg() const {
|
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 353 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
507 unsigned getSubReg() const {
|
| /external/llvm/lib/CodeGen/ |
| MachineInstr.cpp | 80 if (SubIdx && getSubReg())
81 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
89 if (getSubReg()) {
90 Reg = TRI.getSubReg(Reg, getSubReg());
91 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
226 getSubReg() == Other.getSubReg();
268 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
317 OS << PrintReg(getReg(), TRI, getSubReg());
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.cpp | 490 get(Opcode), RI.getSubReg(DestReg, SubIdx));
492 Builder.addReg(RI.getSubReg(SrcReg, SubIdx));
858 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
859 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
875 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
878 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
887 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
888 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
894 .addReg(RI.getSubReg(Src0, AMDGPU::sub0))
895 .addReg(RI.getSubReg(Src1, AMDGPU::sub0)
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 742 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
744 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 191 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
192 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
248 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
249 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
439 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
441 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 272 unsigned getSubReg() const {
336 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
|
