| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips5-wrong-error.s | 9 abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
12 c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
13 c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
14 c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
15 c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
16 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
18 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
[all...] |
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips5-wrong-error.s | 9 abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
12 c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
13 c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
14 c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
15 c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
16 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
18 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
[all...] |
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips5-wrong-error.s | 9 abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
12 c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
13 c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
14 c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
15 c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
16 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
18 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
[all...] |
| /external/llvm/test/MC/ARM/ |
| invalid-fp-armv8.s | 11 @ V8: error: invalid instruction
13 @ V8: error: invalid instruction
15 @ V8: error: invalid instruction
17 @ V8: error: invalid instruction
19 @ V8: error: invalid instruction
21 @ V8: error: invalid instruction
23 @ V8: error: invalid instruction
25 @ V8: error: invalid instruction
27 @ V8: error: invalid instruction
29 @ V8: error: invalid instruction
[all...] |
| directive-arch_extension-simd.s | 20 @ CHECK-V7: error: instruction requires: FPARMv8
22 @ CHECK-V7: error: instruction requires: FPARMv8
25 @ CHECK-V7: error: instruction requires: FPARMv8
27 @ CHECK-V7: error: instruction requires: FPARMv8
30 @ CHECK-V7: error: instruction requires: FPARMv8
32 @ CHECK-V7: error: instruction requires: FPARMv8
34 @ CHECK-V7: error: instruction requires: FPARMv8
36 @ CHECK-V7: error: instruction requires: FPARMv8
38 @ CHECK-V7: error: instruction requires: FPARMv8
40 @ CHECK-V7: error: instruction requires: FPARMv
[all...] |
| thumb2-strd.s | 5 @ CHECK: error: invalid operand for instruction
6 @ CHECK: error: invalid operand for instruction
7 @ CHECK: error: invalid operand for instruction
|
| not-armv4.s | 4 @ CHECK: error: instruction requires: armv5t
7 @ CHECK: error: instruction requires: armv6t2
10 @ CHECK: error: instruction requires: armv6t2
12 @ CHECK: error: instruction requires: armv6t2
|
| /external/smali/smalidea/src/test/java/org/jf/smalidea/dexlib/ |
| SmalideaMethodTest.java | 42 import org.jf.dexlib2.iface.instruction.Instruction;
43 import org.jf.dexlib2.iface.instruction.SwitchElement;
44 import org.jf.dexlib2.iface.instruction.formats.*;
115 List<? extends Instruction> instructions = Lists.newArrayList(impl.getInstructions());
118 Instruction10t instruction = (Instruction10t)instructions.get(0); local
119 Assert.assertEquals(Opcode.GOTO, instruction.getOpcode());
120 Assert.assertEquals(1, instruction.getCodeOffset());
124 Instruction10x instruction = (Instruction10x)instructions.get(1); local
125 Assert.assertEquals(Opcode.RETURN_VOID, instruction.getOpcode())
129 Instruction11n instruction = (Instruction11n)instructions.get(2); local
136 Instruction11x instruction = (Instruction11x)instructions.get(3); local
142 Instruction12x instruction = (Instruction12x)instructions.get(4); local
149 Instruction20t instruction = (Instruction20t)instructions.get(5); local
155 Instruction21c instruction = (Instruction21c)instructions.get(6); local
163 Instruction21ih instruction = (Instruction21ih)instructions.get(7); local
172 Instruction21lh instruction = (Instruction21lh)instructions.get(8); local
180 Instruction21s instruction = (Instruction21s)instructions.get(9); local
187 Instruction21t instruction = (Instruction21t)instructions.get(10); local
194 Instruction22b instruction = (Instruction22b)instructions.get(11); local
202 Instruction22c instruction = (Instruction22c)instructions.get(12); local
211 Instruction22s instruction = (Instruction22s)instructions.get(13); local
219 Instruction22t instruction = (Instruction22t)instructions.get(14); local
227 Instruction22x instruction = (Instruction22x)instructions.get(15); local
234 Instruction23x instruction = (Instruction23x)instructions.get(16); local
242 Instruction30t instruction = (Instruction30t)instructions.get(17); local
248 Instruction31c instruction = (Instruction31c)instructions.get(18); local
255 Instruction31i instruction = (Instruction31i)instructions.get(19); local
262 Instruction32x instruction = (Instruction32x)instructions.get(20); local
269 Instruction35c instruction = (Instruction35c)instructions.get(21); local
280 Instruction3rc instruction = (Instruction3rc)instructions.get(22); local
288 Instruction51l instruction = (Instruction51l)instructions.get(23); local
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| micromips-size-1.l | 2 .*:50: Warning: wrong size instruction in a 32-bit branch delay slot
3 .*:58: Warning: wrong size instruction in a 16-bit branch delay slot
4 .*:64: Warning: wrong size instruction in a 16-bit branch delay slot
5 .*:66: Warning: wrong size instruction in a 16-bit branch delay slot
6 .*:68: Warning: wrong size instruction in a 32-bit branch delay slot
7 .*:70: Warning: wrong size instruction in a 32-bit branch delay slot
8 .*:82: Warning: wrong size instruction in a 32-bit branch delay slot
9 .*:90: Warning: wrong size instruction in a 32-bit branch delay slot
10 .*:92: Warning: wrong size instruction in a 32-bit branch delay slot
|
| mips-gp64-fp64.l | 2 .*:92: Warning: macro instruction expanded into multiple instructions in a branch delay slot
3 .*:96: Warning: macro instruction expanded into multiple instructions in a branch delay slot
4 .*:100: Warning: macro instruction expanded into multiple instructions in a branch delay slot
|
| /external/r8/src/test/java/com/android/tools/r8/utils/ |
| DexInspector.java | 13 import com.android.tools.r8.code.Instruction;
807 InstructionSubject create(Instruction instruction) {
808 if (isInvoke(instruction)) {
809 return new InvokeInstructionSubject(this, instruction);
810 } else if (isFieldAccess(instruction)) {
811 return new FieldAccessInstructionSubject(this, instruction);
813 return new InstructionSubject(this, instruction);
817 boolean isInvoke(Instruction instruction) {
896 protected final Instruction instruction; field in class:DexInspector.InstructionSubject
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| thumb2_it_bad.l | 2 [^:]*:8: Error: branch must be last instruction in IT block -- `beq foo'
3 [^:]*:9: Error: branch must be last instruction in IT block -- `bleq foo'
4 [^:]*:10: Error: branch must be last instruction in IT block -- `blxeq r0'
5 [^:]*:11: Error: instruction not allowed in IT block -- `cbzeq r0,foo'
6 [^:]*:13: Error: branch must be last instruction in IT block -- `bxeq r0'
7 [^:]*:14: Error: branch must be last instruction in IT block -- `tbbeq \[r0,r1\]'
8 [^:]*:15: Error: instruction not allowed in IT block -- `cpsieeq f'
9 [^:]*:17: Error: instruction not allowed in IT block -- `cpseq #0x10'
10 [^:]*:19: Error: instruction is always unconditional -- `bkpteq 0'
11 [^:]*:20: Error: instruction not allowed in IT block -- `setendeq le
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| sse-check-error.l | 17 [ ]*6[ ]+\# SSE instruction
19 .* Error: SSE instruction `addps' is used
21 [ ]*9[ ]+\# SSE2 instruction
23 .* Error: SSE instruction `addpd' is used
25 [ ]*12[ ]+\# SSE3 instruction
27 .* Error: SSE instruction `addsubpd' is used
29 [ ]*15[ ]+\# SSSE3 instruction
31 .* Error: SSE instruction `phaddw' is used
36 .* Error: SSE instruction `blendvpd' is used
39 .* Error: SSE instruction `pcmpgtq' is use
[all...] |
| x86-64-sse-check-error.l | 17 [ ]*6[ ]+\# SSE instruction
19 .* Error: SSE instruction `addps' is used
21 [ ]*9[ ]+\# SSE2 instruction
23 .* Error: SSE instruction `addpd' is used
25 [ ]*12[ ]+\# SSE3 instruction
27 .* Error: SSE instruction `addsubpd' is used
29 [ ]*15[ ]+\# SSSE3 instruction
31 .* Error: SSE instruction `phaddw' is used
36 .* Error: SSE instruction `blendvpd' is used
39 .* Error: SSE instruction `pcmpgtq' is use
[all...] |
| /art/compiler/optimizing/ |
| instruction_simplifier_arm.h | 38 bool TryMergeIntoUsersShifterOperand(HInstruction* instruction);
57 HInstruction* instruction = it.Current(); variable
58 if (instruction->IsInBlock()) {
59 instruction->Accept(this);
64 void VisitAnd(HAnd* instruction) OVERRIDE;
65 void VisitArrayGet(HArrayGet* instruction) OVERRIDE;
66 void VisitArraySet(HArraySet* instruction) OVERRIDE;
67 void VisitMul(HMul* instruction) OVERRIDE;
68 void VisitOr(HOr* instruction) OVERRIDE;
69 void VisitShl(HShl* instruction) OVERRIDE
[all...] |
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/immutable/instruction/ |
| ImmutableInstruction35c.java | 32 package org.jf.dexlib2.immutable.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.Instruction35c;
73 public static ImmutableInstruction35c of(Instruction35c instruction) {
74 if (instruction instanceof ImmutableInstruction35c) {
75 return (ImmutableInstruction35c)instruction;
78 instruction.getOpcode(),
79 instruction.getRegisterCount(),
80 instruction.getRegisterC(),
81 instruction.getRegisterD(),
82 instruction.getRegisterE()
[all...] |
| ImmutableInstruction35mi.java | 32 package org.jf.dexlib2.immutable.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.Instruction35mi;
70 public static ImmutableInstruction35mi of(Instruction35mi instruction) {
71 if (instruction instanceof ImmutableInstruction35mi) {
72 return (ImmutableInstruction35mi)instruction;
75 instruction.getOpcode(),
76 instruction.getRegisterCount(),
77 instruction.getRegisterC(),
78 instruction.getRegisterD(),
79 instruction.getRegisterE()
[all...] |
| ImmutableInstruction35ms.java | 32 package org.jf.dexlib2.immutable.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.Instruction35ms;
70 public static ImmutableInstruction35ms of(Instruction35ms instruction) {
71 if (instruction instanceof ImmutableInstruction35ms) {
72 return (ImmutableInstruction35ms)instruction;
75 instruction.getOpcode(),
76 instruction.getRegisterCount(),
77 instruction.getRegisterC(),
78 instruction.getRegisterD(),
79 instruction.getRegisterE()
[all...] |
| /external/jacoco/org.jacoco.core/src/org/jacoco/core/internal/instr/ |
| DuplicateFrameEliminator.java | 26 private boolean instruction; field in class:DuplicateFrameEliminator
30 instruction = true;
36 if (instruction) {
37 instruction = false;
44 instruction = true;
50 instruction = true;
56 instruction = true;
62 instruction = true;
69 instruction = true;
76 instruction = true
[all...] |
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips3-wrong-error.s | 8 ldl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 ldr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 sdl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
11 sdr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
12 ldle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
13 ldre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
14 sdle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
15 sdre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
16 lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
17 lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
[all...] |
| invalid-mips2.s | 8 addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 bc1fl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 bc1fl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bc1tl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 bc1tl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 beql $14,$s3,12544 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 bgezl $4,-6858 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| invalid-mips32-wrong-error.s | 9 bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
11 bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
12 bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
13 bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
14 bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
15 bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
16 bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/proguard/src/proguard/classfile/instruction/visitor/ |
| InstructionCounter.java | 21 package proguard.classfile.instruction.visitor;
25 import proguard.classfile.instruction.Instruction;
55 Instruction instruction)
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips32-wrong-error.s | 9 bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
11 bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
12 bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
13 bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
14 bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
15 bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
16 bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64r2.s | 8 clo $11,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 drotr32 $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
