| /external/swiftshader/src/Reactor/ |
| Optimizer.cpp | 37 void replace(Ice::Inst *instruction, Ice::Operand *newValue);
38 void deleteInstruction(Ice::Inst *instruction);
39 bool isDead(Ice::Inst *instruction);
41 static const Ice::InstIntrinsicCall *asLoadSubVector(const Ice::Inst *instruction);
42 static const Ice::InstIntrinsicCall *asStoreSubVector(const Ice::Inst *instruction);
43 static bool isLoad(const Ice::Inst &instruction);
44 static bool isStore(const Ice::Inst &instruction);
45 static Ice::Operand *storeAddress(const Ice::Inst *instruction);
46 static Ice::Operand *loadAddress(const Ice::Inst *instruction);
47 static Ice::Operand *storeData(const Ice::Inst *instruction);
[all...] |
| /art/compiler/optimizing/ |
| register_allocator_graph_color.h | 67 * of a phi instruction would prefer to have the same register as at least one of its inputs.)
102 void ProcessInstruction(HInstruction* instruction);
105 // at the position of this instruction.
106 void CheckForFixedInputs(HInstruction* instruction);
108 // If the output of an instruction requires a specific register, split
110 void CheckForFixedOutput(HInstruction* instruction);
113 // Currently depends on instruction processing order.
114 void AddSafepointsFor(HInstruction* instruction);
117 // needed by an instruction.
118 void CheckForTempLiveIntervals(HInstruction* instruction);
[all...] |
| load_store_analysis.h | 60 // used as an environment local of an HDeoptimize instruction.
67 // used as an environment local of an HDeoptimize instruction.
361 ReferenceInfo* GetOrCreateReferenceInfo(HInstruction* instruction) {
362 ReferenceInfo* ref_info = FindReferenceInfoOf(instruction);
365 ref_info = new (GetGraph()->GetArena()) ReferenceInfo(instruction, pos);
371 void CreateReferenceInfoForReferenceType(HInstruction* instruction) {
372 if (instruction->GetType() != Primitive::kPrimNot) {
375 DCHECK(FindReferenceInfoOf(instruction) == nullptr);
376 GetOrCreateReferenceInfo(instruction);
410 void VisitInstanceFieldGet(HInstanceFieldGet* instruction) OVERRIDE
412 CreateReferenceInfoForReferenceType(instruction); variable
443 CreateReferenceInfoForReferenceType(instruction); variable
456 CreateReferenceInfoForReferenceType(instruction); variable
475 CreateReferenceInfoForReferenceType(instruction); variable
479 CreateReferenceInfoForReferenceType(instruction); variable
483 CreateReferenceInfoForReferenceType(instruction); variable
487 CreateReferenceInfoForReferenceType(instruction); variable
491 CreateReferenceInfoForReferenceType(instruction); variable
495 CreateReferenceInfoForReferenceType(instruction); variable
499 CreateReferenceInfoForReferenceType(instruction); variable
503 CreateReferenceInfoForReferenceType(instruction); variable
507 CreateReferenceInfoForReferenceType(instruction); variable
[all...] |
| load_store_elimination.cc | 248 // `instruction` is being removed. Try to see if the null check on it
258 void TryRemovingNullCheck(HInstruction* instruction) {
259 HInstruction* prev = instruction->GetPrevious();
260 if ((prev != nullptr) && prev->IsNullCheck() && (prev == instruction->InputAt(0))) {
261 // Previous instruction is a null check for this instruction. Remove the null check.
288 void VisitGetLocation(HInstruction* instruction,
299 heap_values_for_[instruction->GetBlock()->GetBlockId()];
302 HInstruction* constant = GetDefaultValue(instruction->GetType());
303 removed_loads_.push_back(instruction);
557 HandleInvoke(instruction); variable
562 HandleInvoke(instruction); variable
567 HandleInvoke(instruction); variable
572 HandleInvoke(instruction); variable
[all...] |
| /external/google-breakpad/src/processor/ |
| stackwalker_sparc.cc | 64 // The instruction pointer is stored directly in a register, so pull it
69 frame->instruction = frame->context.pc;
102 uint32_t instruction; local
104 &instruction) || instruction <= 1) {
120 // frame->context.pc is the return address, which is 2 instruction
122 // a CALL instruction then a NOP instruction.
123 // frame_ppc->instruction to 8 less than that. Since all sparc
125 // instruction. This allows source line information to match up with th
[all...] |
| /external/llvm/test/MC/Mips/ |
| set-mips-directives-bad.s | 5 # ll instruction using an unsupported architecture so we just check for "error"
13 dadd $2,$2,$2 # CHECK: error: instruction requires a CPU feature not currently enabled
15 ldxc1 $f8,$2($4) # CHECK: error: instruction requires a CPU feature not currently enabled
17 luxc1 $f19,$2($4) # CHECK: error: instruction requires a CPU feature not currently enabled
19 clo $2,$2 # CHECK: error: instruction requires a CPU feature not currently enabled
21 rotr $2,15 # CHECK: error: instruction requires a CPU feature not currently enabled
23 mod $2, $4, $6 # CHECK: error:instruction requires a CPU feature not currently enabled
26 daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled
29 daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled
31 daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enable
[all...] |
| set-nomacro-micromips.s | 7 # CHECK-NOT: warning: macro instruction expanded into multiple instructions
21 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
23 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
25 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
28 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
30 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
33 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
|
| set-nomacro.s | 3 # CHECK-NOT: warning: macro instruction expanded into multiple instructions
81 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
83 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
85 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
88 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
90 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
92 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
94 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
96 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
99 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instruction
[all...] |
| sym-expr.s | 11 jal __start + 0x4 # CHECK: instruction: [jal, Imm<__start+4>]
12 jal __start + (-0x10) # CHECK: instruction: [jal, Imm<__start-16>]
13 jal (__start + (-0x10)) # CHECK: instruction: [jal, Imm<__start-16>]
|
| /external/lzma/C/ |
| BraIA64.c | 31 UInt64 instruction, instNorm;
local
37 instruction = 0;
39 instruction += (UInt64)data[i + j + bytePos] << (8 * j);
41 instNorm = instruction >> bitRes;
61 instruction &= (1 << bitRes) - 1;
62 instruction |= (instNorm << bitRes);
64 data[i + j + bytePos] = (Byte)(instruction >> (8 * j));
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/immutable/instruction/ |
| ImmutableArrayPayload.java | 32 package org.jf.dexlib2.immutable.instruction;
37 import org.jf.dexlib2.iface.instruction.formats.ArrayPayload;
67 public static ImmutableArrayPayload of(ArrayPayload instruction) {
68 if (instruction instanceof ImmutableArrayPayload) {
69 return (ImmutableArrayPayload)instruction;
72 instruction.getElementWidth(),
73 instruction.getArrayElements());
|
| ImmutablePackedSwitchPayload.java | 32 package org.jf.dexlib2.immutable.instruction;
37 import org.jf.dexlib2.iface.instruction.SwitchElement;
38 import org.jf.dexlib2.iface.instruction.formats.PackedSwitchPayload;
63 public static ImmutablePackedSwitchPayload of(PackedSwitchPayload instruction) {
64 if (instruction instanceof ImmutablePackedSwitchPayload) {
65 return (ImmutablePackedSwitchPayload)instruction;
68 instruction.getSwitchElements());
|
| ImmutableSparseSwitchPayload.java | 32 package org.jf.dexlib2.immutable.instruction;
37 import org.jf.dexlib2.iface.instruction.SwitchElement;
38 import org.jf.dexlib2.iface.instruction.formats.SparseSwitchPayload;
62 public static ImmutableSparseSwitchPayload of(SparseSwitchPayload instruction) {
63 if (instruction instanceof ImmutableSparseSwitchPayload) {
64 return (ImmutableSparseSwitchPayload)instruction;
67 instruction.getSwitchElements());
|
| /external/llvm/test/MC/SystemZ/ |
| insn-bad-zEC12.s | 5 #CHECK: error: {{(instruction requires: vector)?}}
91 #CHECK: error: {{(instruction requires: vector)?}}
93 #CHECK: error: {{(instruction requires: vector)?}}
95 #CHECK: error: {{(instruction requires: vector)?}}
97 #CHECK: error: {{(instruction requires: vector)?}}
99 #CHECK: error: {{(instruction requires: vector)?}}
108 #CHECK: error: {{(instruction requires: vector)?}}
110 #CHECK: error: {{(instruction requires: vector)?}}
112 #CHECK: error: {{(instruction requires: vector)?}}
114 #CHECK: error: {{(instruction requires: vector)?}
[all...] |
| /external/r8/src/main/java/com/android/tools/r8/ir/optimize/ |
| MoveEliminator.java | 6 import com.android.tools.r8.ir.code.Instruction;
20 public boolean shouldBeEliminated(Instruction instruction) {
21 if (instruction.isMove()) {
22 Move move = instruction.asMove();
39 if (instruction.outValue() != null && instruction.outValue().needsRegister()) {
40 Value defined = instruction.outValue();
41 int definedRegister = allocator.getRegisterForValue(defined, instruction.getNumber());
53 if (instruction.isMove())
[all...] |
| /external/llvm/test/MC/Mips/mips32r2/ |
| invalid-msa.s | 8 and.v $w10,$w25,$w29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 bmnz.v $w15,$w2,$w28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 bmz.v $w13,$w11,$w21 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bsel.v $w28,$w7,$w0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 fclass.d $w14,$w27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 fclass.w $w19,$w28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 fexupl.d $w10,$w29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 fexupl.w $w12,$w27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 fexupr.d $w31,$w15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 fexupr.w $w29,$w12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| invalid-dsp.s | 8 absq_s.ph $8,$a0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 absq_s.w $s3,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 addq.ph $s1,$15,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 addq_s.ph $s3,$s6,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 addq_s.w $a2,$8,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 addsc $s8,$15,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 addu.qb $s6,$v1,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 addu_s.qb $s4,$s8,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 addwc $k0,$s6,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 bitrev $14,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/llvm/test/MC/ARM/ |
| invalid-crc32.s | 11 @ CHECK: error: instruction 'crc32cb' is not predicable, but condition code specified
12 @ CHECK: error: instruction 'crc32b' is not predicable, but condition code specified
13 @ CHECK: error: instruction 'crc32ch' is not predicable, but condition code specified
14 @ CHECK: error: instruction 'crc32h' is not predicable, but condition code specified
15 @ CHECK: error: instruction 'crc32cw' is not predicable, but condition code specified
16 @ CHECK: error: instruction 'crc32w' is not predicable, but condition code specified
|
| udf-thumb-2-diagnostics.s | 10 @ CHECK: error: instruction 'udf' is not predicable, but condition code specified
16 @ CHECK: error: instruction requires: arm-mode
22 @ CHECK: error: invalid operand for instruction
|
| diagnostics-noneon.s | 6 @ CHECK-ERRORS: error: instruction requires: NEON
7 @ CHECK-ERRORS: error: instruction requires: NEON
|
| /external/llvm/test/MC/Mips/mips64/ |
| invalid-mips64r2.s | 8 di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 dext $1, $2, 12, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 dextm $1, $2, 21, 43 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 dextu $1, $2, 33, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 dins $1, $2, 12, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 dinsm $1, $2, 21, 43 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 dinsu $1, $2, 33, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips1-wrong-error.s | 8 bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
9 bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
11 lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
12 swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
13 swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| tic4x-dis.c | 60 /* Determine the PC offset for a C[34]x instruction.
355 unsigned long instruction,
363 /* Print instruction name. */
370 if (! tic4x_print_cond (info, EXTRU (instruction, 20, 16)))
374 if (! tic4x_print_cond (info, EXTRU (instruction, 27, 23)))
398 EXTRU (instruction, 15, 0)))
403 tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0));
407 tic4x_print_direct (info, EXTRU (instruction, 15, 0));
411 if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) +
419 tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0)
730 (*info->fprintf_func) (info->stream, "%08lx", instruction); local
742 (*info->fprintf_func) (info->stream, "%08lx", instruction); local
[all...] |
| /external/r8/src/main/java/com/android/tools/r8/ir/code/ |
| NumberConversion.java | 37 com.android.tools.r8.code.Instruction instruction; local
44 instruction = new IntToByte(dest, src);
47 instruction = new IntToChar(dest, src);
50 instruction = new IntToShort(dest, src);
53 instruction = new IntToLong(dest, src);
56 instruction = new IntToFloat(dest, src);
59 instruction = new IntToDouble(dest, src);
68 instruction = new LongToInt(dest, src);
71 instruction = new LongToFloat(dest, src)
[all...] |
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/analysis/ |
| MethodAnalyzer.java | 41 import org.jf.dexlib2.iface.instruction.*;
42 import org.jf.dexlib2.iface.instruction.formats.*;
47 import org.jf.dexlib2.immutable.instruction.*;
84 // This contains all the AnalyzedInstruction instances, keyed by the code unit address of the instruction
88 // Which instructions have been analyzed, keyed by instruction index
93 // This is a dummy instruction that occurs immediately before the first real instruction. We can initialize the
94 // register types for this instruction to the parameter types, in order to have them propagate to all of its
95 // successors, e.g. the first real instruction, the first instructions in any exception handlers covering the first
96 // instruction, etc
247 Instruction instruction = analyzedInstruction.getInstruction(); local
[all...] |
