| /device/linaro/bootloader/edk2/MdePkg/Library/BaseLib/Arm/ |
| Math64.S | 25 stmfd sp!, {r4, r5, r6}
28 mov r4, r6, asl r2
30 orr r4, r4, r0, lsr ip
32 movpl r4, r0, asl r1
35 mov r1, r4
36 ldmfd sp!, {r4, r5, r6}
43 stmfd sp!, {r4, r5, r6}
49 mov r4, r1, lsr r2
53 mov r1, r4
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmHvcLib/Arm/ |
| ArmHvc.S | 22 push {r4-r8}
30 ldr r4, [r0, #16]
42 // A HVC call can return up to 4 values - we do not need to store back r4-r7.
50 // Restore the registers r4-r8
51 pop {r4-r8}
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmSmcLib/Arm/ |
| ArmSmc.S | 21 push {r4-r8}
29 ldr r4, [r0, #16]
41 // A SMC call can return up to 4 values - we do not need to store back r4-r7.
49 // Restore the registers r4-r8
50 pop {r4-r8}
|
| /external/libmpeg2/common/arm/ |
| impeg2_format_conv.s | 117 stmfd sp!, {r4-r8, lr}
119 ldr r4, [sp, #56] @// Load convert_uv_only
121 cmp r4, #1
125 ldr r4, [sp, #28] @// Load u2_height from stack
165 subs r4, r4, #1
172 ldr r4, [sp, #28] @// Load u2_height from stack
186 mov r4, r4, lsr #1
221 subs r4, r4, #
[all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc | 100 {{al, r0, r0, LSL, r4}, false, al, "al r0 r0 LSL r4", "al_r0_r0_LSL_r4"},
108 {{al, r0, r0, LSR, r4}, false, al, "al r0 r0 LSR r4", "al_r0_r0_LSR_r4"},
116 {{al, r0, r0, ASR, r4}, false, al, "al r0 r0 ASR r4", "al_r0_r0_ASR_r4"},
124 {{al, r0, r0, ROR, r4}, false, al, "al r0 r0 ROR r4", "al_r0_r0_ROR_r4"},
132 {{al, r1, r1, LSL, r4}, false, al, "al r1 r1 LSL r4", "al_r1_r1_LSL_r4"}
[all...] |
| test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc | 100 {{vc, r4, r4, ROR, r1}, true, vc, "vc r4 r4 ROR r1", "vc_r4_r4_ROR_r1"},
102 {{vc, r4, r4, LSR, r4}, true, vc, "vc r4 r4 LSR r4", "vc_r4_r4_LSR_r4"}
[all...] |
| test-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc | 99 {{eq, r0, r4}, true, eq, "eq r0 r4", "eq_r0_r4"},
107 {{eq, r1, r4}, true, eq, "eq r1 r4", "eq_r1_r4"},
115 {{eq, r2, r4}, true, eq, "eq r2 r4", "eq_r2_r4"},
123 {{eq, r3, r4}, true, eq, "eq r3 r4", "eq_r3_r4"},
127 {{eq, r4, r0}, true, eq, "eq r4 r0", "eq_r4_r0"}
[all...] |
| test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc | 99 {{eq, r0, r4, 0}, true, eq, "eq r0 r4 0", "eq_r0_r4_0"},
107 {{eq, r1, r4, 0}, true, eq, "eq r1 r4 0", "eq_r1_r4_0"},
115 {{eq, r2, r4, 0}, true, eq, "eq r2 r4 0", "eq_r2_r4_0"},
123 {{eq, r3, r4, 0}, true, eq, "eq r3 r4 0", "eq_r3_r4_0"},
127 {{eq, r4, r0, 0}, true, eq, "eq r4 r0 0", "eq_r4_r0_0"}
[all...] |
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| convolve_neon.s | 34 STMFD r13!, {r4 - r12, r14}
40 ADD r4, r1, r3, LSL #1 @ tmpH address
44 LDRSH r10, [r4] @ *tmpH--
52 SUB r4, r4, #8
53 MOV r9, r4
72 ADD r4, r1, r3, LSL #1 @tmpH address
76 LDRSH r10, [r4], #-2
78 LDRSH r14, [r4]
88 SUB r4, r4, #
[all...] |
| /system/core/libpixelflinger/ |
| col32cb16blend.S | 40 push {r4-r10, lr} // stack ARM regs
48 and r4, r9, r1, lsr #16 // extract blue
51 mov r4, r4, lsl #5 // prescale blue
63 smlabb r8, r8, r5, r4 // dest blue * alpha + src blue
74 pop {r4-r10, pc} // return
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| arch4t.s | 9 ldrsh r4, [r5]
10 ldrsb r4, [r1, r3]
11 ldrsh r1, [r4, r4]!
16 ldrsh r1, [r4, #-250]
24 msr CPSR_x, r4
|
| inst.s | 7 mov r3, r4, lsl #3
33 add r2, r3, r4
38 and r2, r3, r4
43 eor r2, r3, r4
48 sub r2, r3, r4
53 adc r2, r3, r4
58 sbc r2, r3, r4
63 rsb r2, r3, r4
68 rsc r2, r3, r4
73 orr r2, r3, r4
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/d30v/ |
| opt.s | 7 abs r3,r4
52 cmple f0,r4,r5
55 cmple f0,r4,r5
58 cmple f0,r4,r5
61 cmple f0,r4,r5
64 cmple f0,r4,r5
67 cmple f0,r4,r5
70 cmple f1,r4,r5
73 cmple f1,r4,r5
76 # serial because of the r4 dependenc
[all...] |
| bittest.d | 11 8: 04406144 00f00000 ldw.s r6, @\(r5, r4\) || nop
17 38: 047c0105 02201083 moddec r4, 0x5 || bset r1, r2, r3
18 40: 02201083 847c0105 bset r1, r2, r3 -> moddec r4, 0x5
19 48: 02201083 08c04146 bset r1, r2, r3 || joinll.s r4, r5, r6
20 50: 02201083 08c04146 bset r1, r2, r3 || joinll.s r4, r5, r
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/nios2/ |
| movia.d | 15 0+0010 <[^>]*> 01000034 movhi r4,0
17 0+0014 <[^>]*> 21000004 addi r4,r4,0
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/ |
| sh2a.s | 49 mov.b r3,@(4095,r4)
50 mov.w r3,@(4095*2,r4)
51 mov.l r3,@(4095*4,r4)
52 mov.b @(4095,r4),r5
53 mov.w @(4095*2,r4),r5
54 mov.l @(4095*4,r4),r5
76 movu.b @(4095,r3),r4
77 movu.w @(4095*2,r3),r4
79 mulr r0,r4
91 shad r3,r4
[all...] |
| /bionic/libc/arch-arm/generic/bionic/ |
| memcmp.S | 112 stmfd sp!, {r4, lr}
114 .cfi_rel_offset r4, 0
120 mov r4, r0
125 rsb r3, r4, #0
131 1: ldrb r0, [r4], #1
144 eor r0, r4, r1
158 0: pld [r4, #(CACHE_LINE_SIZE * 2)]
160 ldr r0, [r4], #4
163 ldreq r0, [r4], #4
166 ldreq r0, [r4], #
[all...] |
| memcpy.S | 54 * ARM ABI. Since we have to save R0, we might as well save R4
57 stmfd sp!, {r0, r4, lr}
60 .cfi_rel_offset r4, 4
90 ldrbcs r4, [r1], #1
93 strbcs r4, [r0], #1
117 ldmcs r1!, {r4, r5, r6, r7} /* 16 bytes */
119 stmcs r0!, {r4, r5, r6, r7}
157 1: ldmia r1!, { r4-r11 }
166 stmia r0!, { r4-r11 }
185 ldmcs r1!, {r4, r5, r6, r7} /* 16 bytes *
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/arch/ |
| sh2a.s | 15 fmov.d xd4,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <DX_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32}
17 fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
21 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
22 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
23 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
24 addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
26 and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
40 cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
41 cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
42 cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG (…)
[all...] |
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-sh/arch/ |
| sh2a.s | 15 fmov.d xd4,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <DX_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32}
17 fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
21 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
22 add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
23 addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
24 addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
26 and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
40 cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
41 cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
42 cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG (…)
[all...] |
| /external/eigen/unsupported/test/ |
| alignedvector3.cpp | 32 r4(RefType::Random()), r5(RefType::Random());
33 FastType f1(r1), f2(r2), f3(r3), f4(r4), f5(r5);
37 VERIFY_IS_APPROX(f4,r4);
39 VERIFY_IS_APPROX(f4+f1,r4+r1);
40 VERIFY_IS_APPROX(f4-f1,r4-r1);
41 VERIFY_IS_APPROX(f4+f1-f2,r4+r1-r2);
42 VERIFY_IS_APPROX(f4+=f3,r4+=r3);
43 VERIFY_IS_APPROX(f4-=f5,r4-=r5);
44 VERIFY_IS_APPROX(f4-=f5+f1,r4-=r5+r1);
48 VERIFY_IS_APPROX(m1*f4,m1*r4);
[all...] |
| /external/libavc/encoder/arm/ |
| ih264e_evaluate_intra16x16_modes_a9q.s | 85 @r4 = dst_strd,
92 stmfd sp!, {r4-r12, r14} @store register values to stack
103 mov r4, #0
117 moveq r4, #128
142 add r7, r4, r7
212 ldr r4, [sp, #104] @r4 = dst_strd,
247 vst1.32 {d10, d11} , [r2], r4 @0
251 vst1.32 {d12, d13} , [r2], r4 @1
253 vst1.32 {d14, d15} , [r2], r4 @
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ |
| ldivmod.asm | 30 PUSH {r4,lr}
31 ASRS r4,r1,#1
32 EOR r4,r4,r3,LSR #1
43 TST r4,#0x40000000
48 TST r4,#0x80000000
53 POP {r4,pc}
|
| /external/linux-kselftest/tools/testing/selftests/powerpc/math/ |
| vsx_asm.S | 35 std r4,STACK_FRAME_PARAM(1)(sp) # int *threads_starting
44 1: lwarx r4,0,r3
45 addi r4,r4,-1
46 stwcx. r4,0,r3
54 ld r4,STACK_FRAME_PARAM(2)(sp)
55 ld r5,0(r4)
|
| /external/webrtc/webrtc/common_audio/signal_processing/ |
| complex_bit_reverse_arm.S | 20 push {r4-r7}
24 mov r4, #112 @ Number of interations.
29 mov r4, #240 @ Number of interations.
38 mov r4, #0 @ ml
41 rsb r12, r4, r6 @ l > nn - mr
50 and r4, r12, r4
51 add r4, r2 @ mr = (mr & (l - 1)) + l;
52 cmp r4, r3 @ mr <= m ?
55 mov r12, r4, asl #
[all...] |
