| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| srs-arm.l | 2 [^:]*:12: Error: SRS base register must be r13 -- `srsdb r4,#13'
3 [^:]*:13: Error: SRS base register must be r13 -- `srsda r4,#13'
4 [^:]*:14: Error: SRS base register must be r13 -- `srsia r4,#13'
5 [^:]*:15: Error: SRS base register must be r13 -- `srsib r4,#13'
6 [^:]*:24: Error: SRS base register must be r13 -- `srsea r4,#13'
7 [^:]*:25: Error: SRS base register must be r13 -- `srsfd r4,#13'
8 [^:]*:26: Error: SRS base register must be r13 -- `srsfa r4,#13'
9 [^:]*:27: Error: SRS base register must be r13 -- `srsed r4,#13'
10 [^:]*:30: Error: SRS base register must be r13 -- `srs r4,#13'
|
| neon-cond.s | 7 vldreq.32 d3,[r4]
9 vmovge d3, r4, r7
10 vmovcc r3, r4, d30
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/ |
| dv-imply.s | 7 (p1) mov r4 = 2
9 mov r4 = 7
14 mov r4 = 2
16 (p1) mov r4 = 7
20 // prevents RAW on r4.
22 (p1) mov r4 = 2
24 mov r4 = 7
30 (p1) mov r4 = 2
32 mov r4 = 7
38 (p1) mov r4 =
[all...] |
| opc-i.d | 11 6: 40 28 18 8c 38 80 pmpyshr2 r4=r5,r6,0
12 c: 50 30 68 71 pmpyshr2\.u r4=r5,r6,16
14 16: 40 28 18 b4 3a 80 pmpy2\.r r4=r5,r6
15 1c: 50 30 78 75 pmpy2\.l r4=r5,r6
17 26: 40 28 18 20 3a 80 mix1\.r r4=r5,r6
18 2c: 50 30 40 75 mix2\.r r4=r5,r6
20 36: 40 28 18 20 3e 80 mix4\.r r4=r5,r6
21 3c: 50 30 50 74 mix1\.l r4=r5,r6
23 46: 40 28 18 a8 3a 80 mix2\.l r4=r5,r6
24 4c: 50 30 50 7c mix4\.l r4=r5,r
[all...] |
| opc-x.s | 11 movl r4 = 0
12 movl r4 = 0xffffffffffffffff
13 movl r4 = 0x1234567890abcdef
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| omxVCM4P10_TransformDequantChromaDCFromPair_s.S | 31 push {r4-r10, lr}
40 ldrbne r4, [r9], #2
42 ldrsbeq r4, [r9], #1
43 orrne r4, r4, r5, lsl #8
46 strh r4, [r1, r7]
48 ldmia r1, {r3, r4}
55 saddsubx r4, r4, r4
[all...] |
| armVCM4P10_Average_4x_Align_unsafe_s.S | 30 PUSH {r4-r6,lr}
39 UHSUB8 r4,r11,lr
42 EOR r4,r4,r7
43 STR r4,[r2],r3
51 UHSUB8 r4,r11,lr
54 EOR r4,r4,r7
55 STR r4,[r2],r3
56 POP {r4-r6,pc
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cris/ |
| prefix.s | 10 move.b [r5],r4
13 move.w [r6+],r4
16 move.b [r5],r4
19 move.w [r6+],r4
22 move.b [r5],r4
25 move.w [r6+],r4
28 move.b [r5],r4
31 move.w [r6],r4
37 bdap.b 0,r4
41 move.b [r5],r4
[all...] |
| addi.s | 14 addi r4.b,r4
15 addi r4.w,r4
16 addi r4.d,r4
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/BaseMemoryLibStm/Arm/ |
| SetMem.S | 44 stmfd sp!, {r4-r11, lr}
58 and r4, r2, #0xff
59 orr r4, r4, r4, LSL #8
60 orr r4, r4, r4, LSL #16
61 mov r5, r4
62 mov r6, r4
[all...] |
| /device/linaro/hikey/l-loader/ |
| start.S | 44 ldr r4, =0xf6504000 @ ACPU_CTRL register base
49 str r6, [r4, r5]
51 ldr r0, [r4, r5]
58 ldr r0, [r4, r5] @ Load ACPU_SC_CPUx_CTRL
60 str r0, [r4, r5] @ Save to ACPU_SC_CPUx_CTRL
61 ldr r0, [r4, r5]
71 ldr r4, =0xf70100e0 @ UART2_RXD IOMG register
73 str r0, [r4]
74 str r0, [r4, #4] @ UART2_TXD IOMG register
75 ldr r0, [r4]
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/score/ |
| rD_rA_rB.d | 12 4: 2540 add! r5, r4
13 6: 2540 add! r5, r4
14 8: 2f40 add! r15, r4
15 a: 2f40 add! r15, r4
21 18: 83579011 add.c r26, r23, r4
26 24: 0549 addc! r5, r4
27 26: 0549 addc! r5, r4
28 28: 0f49 addc! r15, r4
29 2a: 0f49 addc! r15, r4
35 38: 83579013 addc.c r26, r23, r4
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/d10v/ |
| instruction_packing.s | 19 add r4,r5 || ld r2,@r3
20 add r4,r5 || bra.s test_end
23 add r4,r5 || sra r0,r1
24 add r4,r5 || mulx a0, r6, r7
27 ld r2,@r3 || add r4,r5
28 bra.s test_end || add r4,r5
31 sra r0,r1 || add r4,r5
32 mulx a0, r6, r7 || add r4,r5
43 add r4,r5 -> ld r2,@r3
44 add r4,r5 -> bra.s test_en
[all...] |
| instruction_packing.d | 21 14: 30 23 02 8a ld r2, @r3 || add r4, r5
22 18: 24 0f 82 8a bra.s 94 <test_end> || add r4, r5
25 1c: 01 45 24 02 add r4, r5 || sra r0, r1
26 20: 01 45 2c ce add r4, r5 || mulx a0, r6, r7
29 24: 30 23 02 8a ld r2, @r3 || add r4, r5
30 28: 24 0d 82 8a bra.s 94 <test_end> || add r4, r5
33 2c: 01 45 24 02 add r4, r5 || sra r0, r1
34 30: 01 45 2c ce add r4, r5 || mulx a0, r6, r7
45 44: 41 45 60 46 add r4, r5 -> ld r2, @r3
46 48: 41 45 48 13 add r4, r5 -> bra.s 94 <test_end
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/hppa/reloc/ |
| labelopbug.s | 8 copy %r4,%r1
9 copy %r30,%r4
11 stw %r30,12(%r4)
15 stw %r19,8(%r4)
24 ldo -8(%r4),%r4
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/nios2/ |
| warn_nobreak.s | 5 add ba, r3, r4
6 add bt, r3, r4
8 add ba, r3, r4
9 add bt, r3, r4
11 add ba, r3, r4
12 add bt, r3, r4
|
| /external/llvm/test/MC/ARM/ |
| neon-vld-vst-align.s | 5 vld1.8 {d0}, [r4]
6 vld1.8 {d0}, [r4:16]
7 vld1.8 {d0}, [r4:32]
8 vld1.8 {d0}, [r4:64]
9 vld1.8 {d0}, [r4:128]
10 vld1.8 {d0}, [r4:256]
12 @ CHECK: vld1.8 {d0}, [r4] @ encoding: [0x24,0xf9,0x0f,0x07]
14 @ CHECK-ERRORS: vld1.8 {d0}, [r4:16]
17 @ CHECK-ERRORS: vld1.8 {d0}, [r4:32]
19 @ CHECK: vld1.8 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x07
[all...] |
| /frameworks/native/opengl/libagl/ |
| iterators.S | 51 stmfd sp!, {r4, r5, r6, r7, r8, lr}
52 ldr r4, [sp, #4*6]
56 sub r4, r4, r2
59 mov r4, r4, asr r12
63 smull r8, lr, r4, r5
65 smull r6, r7, r4, r12
71 ldr r4, [r0, #20] // m_x1
77 umull r8, r0, r4, r
[all...] |
| /bionic/libc/arch-arm/syscalls/ |
| ___fsetxattr.S | 7 stmfd sp!, {r4, r5, r6, r7}
9 .cfi_rel_offset r4, 0
13 ldmfd ip, {r4, r5, r6}
16 ldmfd sp!, {r4, r5, r6, r7}
|
| ___mremap.S | 7 stmfd sp!, {r4, r5, r6, r7}
9 .cfi_rel_offset r4, 0
13 ldmfd ip, {r4, r5, r6}
16 ldmfd sp!, {r4, r5, r6, r7}
|
| __arm_fadvise64_64.S | 7 stmfd sp!, {r4, r5, r6, r7}
9 .cfi_rel_offset r4, 0
13 ldmfd ip, {r4, r5, r6}
16 ldmfd sp!, {r4, r5, r6, r7}
|
| __epoll_pwait.S | 7 stmfd sp!, {r4, r5, r6, r7}
9 .cfi_rel_offset r4, 0
13 ldmfd ip, {r4, r5, r6}
16 ldmfd sp!, {r4, r5, r6, r7}
|
| __llseek.S | 7 stmfd sp!, {r4, r5, r6, r7}
9 .cfi_rel_offset r4, 0
13 ldmfd ip, {r4, r5, r6}
16 ldmfd sp!, {r4, r5, r6, r7}
|
| __mmap2.S | 7 stmfd sp!, {r4, r5, r6, r7}
9 .cfi_rel_offset r4, 0
13 ldmfd ip, {r4, r5, r6}
16 ldmfd sp!, {r4, r5, r6, r7}
|
| __ppoll.S | 7 stmfd sp!, {r4, r5, r6, r7}
9 .cfi_rel_offset r4, 0
13 ldmfd ip, {r4, r5, r6}
16 ldmfd sp!, {r4, r5, r6, r7}
|
