| /external/libhevc/common/arm/ |
| ihevc_intra_pred_luma_mode_18_34.s | 127 moveq r6,#1
128 movne r6,#-1
133 vld1.8 {d0},[r8],r6
135 vld1.8 {d1},[r8],r6
137 vld1.8 {d2},[r8],r6
138 vld1.8 {d3},[r8],r6
140 vld1.8 {d4},[r8],r6
141 vld1.8 {d5},[r8],r6
142 vld1.8 {d6},[r8],r6
144 vld1.8 {d7},[r8],r6
[all...] |
| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/mme/ |
| com9097.mme | 67 mov $r6 (extrinsrt 0x0 $r1 0x0 0x4 0x2)
69 maddr $r6 (add $r6 0x1701)
96 mov $r6 0x60
100 mov $r6 0x200
106 mov $r6 0x0
109 send $r6
135 mov $r6 0x60
139 mov $r6 0x200
145 mov $r6 0x
[all...] |
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| convolve_opt.s | 41 MOV r6, r0 @ tmpX = x
42 LDRSH r9, [r6], #2 @ *tmpX++
50 LDRSH r9, [r6], #2 @ *tmpX++
52 LDRSH r12, [r6], #2 @ *tmpX++
56 LDRSH r9, [r6], #2 @ *tmpX++
58 LDRSH r12, [r6], #2 @ *tmpX++
76 MOV r6, r0
77 LDRSH r9, [r6], #2 @ *tmpX++
79 LDRSH r12, [r6], #2
89 LDRSH r9, [r6], #2 @ *tmpX+
[all...] |
| cor_h_vec_opt.s | 31 @r6 ---- cor_2[]
48 MOV r6, #0 @L_sum2 = 0
59 MLA r6, r12, r14, r6
63 MOV r6, r6, LSL #2 @L_sum2 = (L_sum2 << 2)
67 ADD r10, r6, r14
70 MOV r6, r10, ASR #16
76 MUL r14, r6, r11
78 MOV r6, r14, ASR #1
[all...] |
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| vpx_convolve_avg_neon_asm.asm | 19 push {r4-r6, lr}
21 mov r6, r2
39 vld1.8 {q8-q9}, [r6@128]!
40 vld1.8 {q10-q11}, [r6@128], r4
49 pop {r4-r6, pc}
54 vld1.8 {q8-q9}, [r6@128], r3
55 vld1.8 {q10-q11}, [r6@128], r3
60 pld [r6]
62 pld [r6, r3]
68 pop {r4-r6, pc
[all...] |
| /bionic/libc/arch-arm/bionic/ |
| syscall.S | 33 stmfd sp!, {r4, r5, r6, r7}
37 .cfi_rel_offset r6, 8
43 ldmfd ip, {r3, r4, r5, r6}
45 ldmfd sp!, {r4, r5, r6, r7}
|
| /external/valgrind/none/tests/x86/ |
| incdec_alt.c | 7 int r1,r2,r3,r4,r5,r6,r7,r8,a1,a2; variable
40 "\tpopl " VG_SYM(r6) "\n"
58 r1=r2=r3=r4=r5=r6=r7=r8=0;
65 printf("0x%08x\n",r6);
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| cor_h_vec_neon.s | 32 @r6 ---- cor_2[]
49 MOV r6, #0 @L_sum2 = 0
60 MLA r6, r12, r14, r6
64 MOV r6, r6, LSL #2 @L_sum2 = (L_sum2 << 2)
68 ADD r10, r6, r14
71 MOV r6, r10, ASR #16
77 MUL r14, r6, r11
79 MOV r6, r14, ASR #1
[all...] |
| Norm_Corr_neon.s | 32 @ r6 --- corr_norm[]
98 QADD r6, r9, r10
99 QADD r6, r6, r6
100 QADD r9, r6, r7 @L_tmp = (L_tmp << 1) + 1;
102 SUB r6, r7, #1 @exp = norm_l(L_tmp)
103 RSB r7, r6, #32 @exp = 32 - exp
104 MOV r6, r7, ASR #1
105 RSB r7, r6, #0 @scale = -(exp >> 1
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| mrs-msr-arm-v6.s | 7 mrs r6, spsr
13 msr spsr, r6
|
| mrs-msr-arm-v7-a.s | 7 mrs r6, spsr
13 msr spsr, r6
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cris/ |
| shexpr-1.s | 5 move.d ((0x17<<23)+((0xfede4194/8192)<<4)+8),r6
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/ |
| operands.s | 4 zxt2 r4 = r5, r6
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/nios2/ |
| etbt.d | 9 0+0000 <[^>]*> c9b1883a add et,bt,r6
10 0+0004 <[^>]*> c9b1883a add et,bt,r6
|
| mul.d | 9 0+0000 <[^>]*> 2989383a mul r4,r5,r6
17 0+001c <[^>]*> 2988f83a mulxss r4,r5,r6
18 0+0020 <[^>]*> 2988b83a mulxsu r4,r5,r6
19 0+0024 <[^>]*> 2988383a mulxuu r4,r5,r6
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/s390/ |
| zarch-machine.s | 6 asi 5555(%r6),-42
|
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc | 96 {{{ge, r1, r1, LSL, r6}, true, ge, "ge r1 r1 LSL r6", "ge_r1_r1_LSL_r6"},
103 {{le, r6, r6, ASR, r6}, true, le, "le r6 r6 ASR r6", "le_r6_r6_ASR_r6"},
104 {{hi, r6, r6, ROR, r5}, true, hi, "hi r6 r6 ROR r5", "hi_r6_r6_ROR_r5"}
[all...] |
| test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc | 145 {{al, r0, r6, 0}, false, al, "al r0 r6 0", "al_r0_r6_0"},
146 {{al, r0, r6, 1}, false, al, "al r0 r6 1", "al_r0_r6_1"},
147 {{al, r0, r6, 2}, false, al, "al r0 r6 2", "al_r0_r6_2"},
148 {{al, r0, r6, 3}, false, al, "al r0 r6 3", "al_r0_r6_3"},
149 {{al, r0, r6, 4}, false, al, "al r0 r6 4", "al_r0_r6_4"}
[all...] |
| test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc | [all...] |
| test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc | 102 {{al, r0, r0, LSL, r6}, false, al, "al r0 r0 LSL r6", "al_r0_r0_LSL_r6"},
110 {{al, r0, r0, LSR, r6}, false, al, "al r0 r0 LSR r6", "al_r0_r0_LSR_r6"},
118 {{al, r0, r0, ASR, r6}, false, al, "al r0 r0 ASR r6", "al_r0_r0_ASR_r6"},
126 {{al, r0, r0, ROR, r6}, false, al, "al r0 r0 ROR r6", "al_r0_r0_ROR_r6"},
134 {{al, r1, r1, LSL, r6}, false, al, "al r1 r1 LSL r6", "al_r1_r1_LSL_r6"}
[all...] |
| test-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc | 99 {{ls, r1, r6, 0}, true, ls, "ls r1 r6 0", "ls_r1_r6_0"},
102 {{vs, r5, r6, 7}, true, vs, "vs r5 r6 7", "vs_r5_r6_7"},
106 {{lt, r6, r7, 1}, true, lt, "lt r6 r7 1", "lt_r6_r7_1"},
116 {{ls, r6, r6, 4}, true, ls, "ls r6 r6 4", "ls_r6_r6_4"}
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/z8k/ |
| translate-ops.d | 10 0: b828 0640 trdb @rr2,@rr4,r6
11 4: b82c 0640 trdrb @rr2,@rr4,r6
17 1c: b826 064e trtirb @rr2,@rr4,r6
|
| /frameworks/av/media/libstagefright/codecs/m4v_h263/dec/src/ |
| idct.cpp | 131 int32 r0, r1, r2, r3, r4, r5, r6, r7, r8; /* butterfly nodes */ local
155 r6 = blk[B_SIZE * 5 + i];
158 if (!(r1 | r2 | r3 | r4 | r5 | r6 | r7))
187 r8 = W3 * (r6 + r7);
188 r6 = (r8 - (W3 - W5) * r6);
199 r1 = r4 + r6;
200 r4 -= r6;
201 r6 = r5 + r7;
221 tmpBLK32[(3<<3) + i] = (r8 + r6) >> 8
353 int32 r0, r1, r2, r3, r4, r5, r6, r7, r8; \/* butterfly nodes *\/ local
[all...] |
| /frameworks/av/media/libstagefright/codecs/mp3dec/src/asm/ |
| pvmp3_polyphase_filter_window_gcc.s | 72 ldr r6,[r12,#0x780]
74 smlal r2,r11,lr,r6
78 smull r6,r5,r2,r6
83 smlal r6,r9,r5,r7
84 smull r6,r2,r5,r8
91 ldr r6,[r12,#0x680]
93 smlal lr,r11,r2,r6
97 smull r6,r5,r2,r6
[all...] |
| /external/compiler-rt/lib/tsan/rtl/ |
| tsan_rtl_ppc64.S | 54 ld r6,-28696(r13)
56 xor r5,r6,r5
60 xor r0,r6,r0
104 addi r6,r5,16
107 stvx v21,0,r6
108 addi r6,r6,32
111 stvx v23,0,r6
112 addi r6,r6,3
[all...] |
