| /art/runtime/arch/mips/ |
| instruction_set_features_mips.cc | 50 static void GetFlagsFromCppDefined(bool* mips_isa_gte2, bool* r6, bool* fpu_32bit, bool* msa) {
67 *r6 = true;
69 *r6 = false;
80 bool r6; local
82 GetFlagsFromCppDefined(&mips_isa_gte2, &r6, &fpu_32bit, &msa);
85 // Only care if it is R1, R2, R5 or R6 and we assume all CPUs will have a FP unit.
90 r6 = (variant[kPrefixLength] >= '6');
97 // Note, we get FPU bitness and R6-ness from the build (using cpp defines, see above)
99 // sufficient for most purposes. That is, "default" should work for both R2 and R6.
107 return MipsFeaturesUniquePtr(new MipsInstructionSetFeatures(fpu_32bit, mips_isa_gte2, r6, msa))
113 bool r6 = (bitmap & kR6) != 0; local
121 bool r6; local
131 bool r6; local
216 bool r6 = r6_; local
[all...] |
| /external/libavc/encoder/arm/ |
| ih264e_evaluate_intra4x4_modes_a9q.s | 112 @r6 = u4_intra_mode,
160 subs r6, r1, #0
162 lslne r6, r0, #2
164 moveq r6, r0 @
166 add r9, r6, r9
168 subs r6, r11, r9
183 subs r6, r1, #1
186 lslne r6, r0, #2
190 moveq r6, r0 @
191 add r9, r6, r
[all...] |
| /external/llvm/test/MC/ARM/ |
| directive-arch-armv4.s | 32 mul r4, r5, r6
33 mla r4, r5, r6, r3
34 smull r4, r5, r6, r3
35 umull r4, r5, r6, r3
36 smlal r4, r5, r6, r3
37 umlal r4, r5, r6, r3
|
| directive-fpu-instrs.s | 11 str r6, [r7, #264]
12 mov r6, r5
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cris/ |
| rd-v32s-4.s | 7 move $r6,$p2
12 move $r6,$p7
17 move $r6,$p12
24 move $p2,$r6
29 move $p7,$r6
34 move $p12,$r6
58 move $p2,[$r6]
63 move $p7,[$r6]
68 move $p12,[$r6]
75 move [$r6],$p
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/crx/ |
| load_stor_insn.s | 14 loadb 0(sp), r6
15 loadb 0x456(r6), r7
30 loadw 0(sp), r6
31 loadw 0456(r6), r7
46 loadd 0(sp), r6
47 loadd 0x100(r6), r7
63 storb r6, 0(sp)
64 storb r7, 0x456(r6)
81 storw r6, 0(sp)
82 storw r7, 0456(r6)
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/v850/ |
| compare.s | 5 cmp r5,r6
6 cmp 5,r6
27 tst r5,r6
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-xc16x/ |
| absrel.s | 4 mov r6,#0xf
8 mov r6,#0xd
13 mov r6,#0xf
|
| /external/tremolo/Tremolo/ |
| bitwiseARM.s | 67 STMFD r13!,{r5,r6}
79 LDRLT r6,[r3] @ r6 = ptr[1]
82 ORRLT r10,r10,r6,LSL r12 @ r10= first bitsLeftInSeg bits+crap
97 LDMIA r11,{r6,r12,r14} @ r6 = buffer
100 LDR r6,[r6] @ r6 = buffer->data
103 ADD r6,r6,r12 @ r6 = buffer->data+begi
[all...] |
| /external/python/cpython2/Modules/_ctypes/libffi/src/moxie/ |
| eabi.S | 45 push $sp, $r6
59 mov $r6, $r4 /* Save result buffer */
86 st.l ($r6), $r0
90 st.l ($r6), $r0
91 sto.l 4($r6), $r1
96 ldo.l $r6, -4($fp)
|
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rdlow-rnlow-rmlow-t32.cc | 101 {{al, r0, r6, r0}, false, al, "al r0 r6 r0", "al_r0_r6_r0"},
109 {{al, r1, r6, r1}, false, al, "al r1 r6 r1", "al_r1_r6_r1"},
117 {{al, r2, r6, r2}, false, al, "al r2 r6 r2", "al_r2_r6_r2"},
125 {{al, r3, r6, r3}, false, al, "al r3 r6 r3", "al_r3_r6_r3"},
133 {{al, r4, r6, r4}, false, al, "al r4 r6 r4", "al_r4_r6_r4"}
[all...] |
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| Dot_p_opt.s | 39 LDR r6, [r0], #4
42 SMLABB r4, r6, r7, r4
44 SMLATT r4, r6, r7, r4
46 LDR r6, [r0], #4
53 SMLABB r4, r6, r7, r4
55 SMLATT r4, r6, r7, r4
|
| /external/boringssl/ios-arm/crypto/fipsmodule/ |
| sha1-armv4-large.S | 32 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
34 ldmia r0,{r3,r4,r5,r6,r7}
40 mov r6,r6,ror#30
50 eor r10,r5,r6 @ F_xx_xx
57 eor r10,r5,r6 @ F_xx_xx
65 eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
72 add r6,r8,r6,ror#2 @ E+=K_00_19
77 add r6,r6,r7,ror#27 @ E+=ROR(A,27
[all...] |
| /external/boringssl/linux-arm/crypto/fipsmodule/ |
| sha1-armv4-large.S | 31 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
33 ldmia r0,{r3,r4,r5,r6,r7}
39 mov r6,r6,ror#30
49 eor r10,r5,r6 @ F_xx_xx
56 eor r10,r5,r6 @ F_xx_xx
64 eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
71 add r6,r8,r6,ror#2 @ E+=K_00_19
76 add r6,r6,r7,ror#27 @ E+=ROR(A,27
[all...] |
| /external/v8/src/ic/ppc/ |
| access-compiler-ppc.cc | 27 Register load_registers[] = {receiver, name, r6, r3, r7};
31 Register store_registers[] = {receiver, name, r6, r7};
|
| /external/v8/src/ic/s390/ |
| access-compiler-s390.cc | 28 Register load_registers[] = {receiver, name, r5, r2, r6};
32 Register store_registers[] = {receiver, name, r5, r6};
|
| /prebuilts/go/darwin-x86/src/runtime/cgo/ |
| gcc_arm.S | 27 push {r4, r5, r6, r7, r8, r9, r10, r11, ip, lr}
37 pop {r4, r5, r6, r7, r8, r9, r10, r11, ip, pc}
|
| /prebuilts/go/linux-x86/src/runtime/cgo/ |
| gcc_arm.S | 27 push {r4, r5, r6, r7, r8, r9, r10, r11, ip, lr}
37 pop {r4, r5, r6, r7, r8, r9, r10, r11, ip, pc}
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| thumb2_pool.s | 6 ldr r6, =0x12345678
8 ldr.w r6, =0x12345678
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cr16/ |
| cbitb_test.s | 18 cbitb $3,[r12]0xa7a(r6,r5)
19 cbitb $3,[r12]0xa7a(r7,r6)
26 cbitb $3,[r13]0xa7a(r6,r5)
27 cbitb $3,[r13]0xa7a(r7,r6)
31 cbitb $1,[r12]0x17a(r6,r5)
32 cbitb $1,[r13]0x134(r6,r5)
35 cbitb $3,[r12]0xabcd(r6,r5)
36 cbitb $3,[r13]0xbcde(r6,r5)
|
| jcc_test.d | 15 a: c5 0a jlt \(r6,r5\)
16 c: 66 0a jgt \(r7,r6\)
23 1a: e5 0a jump \(r6,r5\)
24 1c: f5 0a jusr \(r6,r5\)
|
| pop_test.s | 8 pop $2,r6,RA
18 pop $2,r6
|
| popret_test.s | 8 popret $2,r6,RA
18 popret $2,r6
|
| sbitb_test.s | 18 sbitb $3,[r12]0xa7a(r6,r5)
19 sbitb $3,[r12]0xa7a(r7,r6)
26 sbitb $3,[r13]0xa7a(r6,r5)
27 sbitb $3,[r13]0xa7a(r7,r6)
31 sbitb $1,[r12]0x17a(r6,r5)
32 sbitb $1,[r13]0x134(r6,r5)
35 sbitb $3,[r12]0xabcd(r6,r5)
36 sbitb $3,[r13]0xbcde(r6,r5)
|
| sub_test.s | 19 subb r5,r6
20 subb r6,r7
37 subcb r5,r6
38 subcb r6,r7
55 subcw r5,r6
56 subcw r6,r7
73 subw r5,r6
74 subw r6,r7
|
