| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-rn-operand-imm12-t32.cc | 106 {{al, r6, r9, 3696}, false, al, "al r6 r9 3696", "al_r6_r9_3696"},
108 {{al, r6, r1, 2016}, false, al, "al r6 r1 2016", "al_r6_r1_2016"},
124 {{al, r8, r6, 2}, false, al, "al r8 r6 2", "al_r8_r6_2"},
142 {{al, r7, r6, 3397}, false, al, "al r7 r6 3397", "al_r7_r6_3397"},
143 {{al, r14, r6, 3921}, false, al, "al r14 r6 3921", "al_r14_r6_3921"}
[all...] |
| test-assembler-cond-rd-rn-a32.cc | 102 {{hi, r6, r12}, false, al, "hi r6 r12", "hi_r6_r12"},
107 {{gt, r8, r6}, false, al, "gt r8 r6", "gt_r8_r6"},
117 {{hi, r6, r0}, false, al, "hi r6 r0", "hi_r6_r0"},
124 {{lt, r10, r6}, false, al, "lt r10 r6", "lt_r10_r6"},
127 {{pl, r10, r6}, false, al, "pl r10 r6", "pl_r10_r6"}
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 131 {{al, r14, r6, r10, LSR, 32},
134 "al r14 r6 r10 LSR 32",
136 {{al, r9, r6, r3, LSR, 13},
139 "al r9 r6 r3 LSR 13",
141 {{al, r14, r4, r6, LSR, 31},
144 "al r14 r4 r6 LSR 31",
161 {{al, r6, r10, r0, LSR, 8},
164 "al r6 r10 r0 LSR 8",
186 {{al, r11, r6, r14, ASR, 31},
189 "al r11 r6 r14 ASR 31"
[all...] |
| test-assembler-cond-rd-rn-operand-rm-t32.cc | 135 {{al, r11, r6, r9}, false, al, "al r11 r6 r9", "al_r11_r6_r9"},
140 {{al, r10, r6, r7}, false, al, "al r10 r6 r7", "al_r10_r6_r7"},
142 {{al, r6, r8, r5}, false, al, "al r6 r8 r5", "al_r6_r8_r5"},
143 {{al, r5, r10, r6}, false, al, "al r5 r10 r6", "al_r5_r10_r6"},
146 {{al, r5, r6, r4}, false, al, "al r5 r6 r4", "al_r5_r6_r4"}
[all...] |
| test-assembler-cond-rd-operand-rn-shift-rs-t32.cc | 112 {{al, r6, r11, ASR, r8}, false, al, "al r6 r11 ASR r8", "al_r6_r11_ASR_r8"},
114 {{al, r10, r6, ASR, r7}, false, al, "al r10 r6 ASR r7", "al_r10_r6_ASR_r7"},
144 {{al, r6, r13, ROR, r2}, false, al, "al r6 r13 ROR r2", "al_r6_r13_ROR_r2"},
145 {{al, r4, r6, LSL, r6}, false, al, "al r4 r6 LSL r6", "al_r4_r6_LSL_r6"}
[all...] |
| test-assembler-cond-rd-rn-operand-rm-a32.cc | 135 {{pl, r6, r1, r5}, false, al, "pl r6 r1 r5", "pl_r6_r1_r5"},
136 {{ge, r1, r12, r6}, false, al, "ge r1 r12 r6", "ge_r1_r12_r6"},
141 {{cc, r8, r6, r11}, false, al, "cc r8 r6 r11", "cc_r8_r6_r11"},
147 {{vs, r8, r6, r7}, false, al, "vs r8 r6 r7", "vs_r8_r6_r7"},
155 {{gt, r6, r7, r3}, false, al, "gt r6 r7 r3", "gt_r6_r7_r3"}
[all...] |
| test-assembler-cond-rd-memop-rs-a32.cc | 104 const TestData kTests[] = {{{pl, r8, r11, plus, r6, Offset},
107 "pl r8 r11 plus r6 Offset",
114 {{vs, r2, r6, plus, r14, Offset},
117 "vs r2 r6 plus r14 Offset",
124 {{ge, r14, r6, plus, r14, Offset},
127 "ge r14 r6 plus r14 Offset",
149 {{cc, r11, r10, plus, r6, Offset},
152 "cc r11 r10 plus r6 Offset",
154 {{lt, r9, r6, plus, r1, Offset},
157 "lt r9 r6 plus r1 Offset"
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 161 {{al, r6, r13, r3, ROR, 1},
164 "al r6 r13 r3 ROR 1",
191 {{al, r3, r1, r6, ROR, 3},
194 "al r3 r1 r6 ROR 3",
201 {{al, r2, r0, r6, ROR, 3},
204 "al r2 r0 r6 ROR 3",
226 {{al, r10, r3, r6, ROR, 1},
229 "al r10 r3 r6 ROR 1",
231 {{al, r6, r14, r2, ROR, 13},
234 "al r6 r14 r2 ROR 13"
[all...] |
| test-assembler-cond-rd-pc-operand-imm8-t32.cc | 96 {{al, r6, pc, 78}, false, al, "al r6 pc 78", "al_r6_pc_78"},
100 {{al, r6, pc, 150}, false, al, "al r6 pc 150", "al_r6_pc_150"},
104 {{al, r6, pc, 49}, false, al, "al r6 pc 49", "al_r6_pc_49"},
106 {{al, r6, pc, 107}, false, al, "al r6 pc 107", "al_r6_pc_107"},
109 {{al, r6, pc, 54}, false, al, "al r6 pc 54", "al_r6_pc_54"}
[all...] |
| /external/llvm/test/MC/ARM/ |
| basic-thumb-instructions.s | 26 adcs r4, r6
28 @ CHECK: adcs r4, r6 @ encoding: [0x74,0x41]
162 bics r1, r6
164 @ CHECK: bics r1, r6 @ encoding: [0xb1,0x43]
221 cmp r6, #32
225 @ CHECK: cmp r6, #32 @ encoding: [0x20,0x2e]
250 ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7}
254 @ CHECK: ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7} @ encoding: [0xff,0xcb]
263 ldr r2, [r6, #32]
271 @ CHECK: ldr r2, [r6, #32] @ encoding: [0x32,0x6a
[all...] |
| dot-req.s | 10 fred .req r6
14 @ CHECK: mov r1, r6 @ encoding: [0x06,0x10,0xa0,0xe1]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| basic-thumb-instructions.s | 25 adcs r4, r6
27 @ CHECK: adcs r4, r6 @ encoding: [0x74,0x41]
141 bics r1, r6
143 @ CHECK: bics r1, r6 @ encoding: [0xb1,0x43]
196 cmp r6, #32
200 @ CHECK: cmp r6, #32 @ encoding: [0x20,0x2e]
215 ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7}
219 @ CHECK: ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7} @ encoding: [0xff,0xcb]
228 ldr r2, [r6, #32]
236 @ CHECK: ldr r2, [r6, #32] @ encoding: [0x32,0x6a
[all...] |
| basic-thumb2-instructions.s | 43 adc r4, r5, r6
44 adcs r4, r5, r6
52 @ CHECK: adc.w r4, r5, r6 @ encoding: [0x45,0xeb,0x06,0x04]
53 @ CHECK: adcs.w r4, r5, r6 @ encoding: [0x55,0xeb,0x06,0x04]
73 add r12, r6, #0x100
74 addw r12, r6, #0x100
85 @ CHECK: add.w r12, r6, #256 @ encoding: [0x06,0xf5,0x80,0x7c]
86 @ CHECK: addw r12, r6, #256 @ encoding: [0x06,0xf2,0x00,0x1c]
96 adds.w r0, r3, r6, lsr #25
102 @ CHECK: adds.w r0, r3, r6, lsr #25 @ encoding: [0x13,0xeb,0x56,0x60
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cr16/ |
| storb_test.s | 37 storb r6,0xA1234(r1,r0)
42 storb r6,-0xA1234(r1,r0)
53 storb r5,0xA1234(r6,r5)
59 storb r5,-0xA1234(r6,r5)
72 storb r6,[r13]0xfffff(r1,r0)
95 storb $3,[r12]0xa7a(r6,r5)
96 storb $3,[r12]0xa7a(r7,r6)
103 storb $3,[r13]0xa7a(r6,r5)
104 storb $3,[r13]0xa7a(r7,r6)
108 storb $1,[r12]0x17a(r6,r5)
[all...] |
| storw_test.s | 37 storw r6,0xA1234(r1,r0)
42 storw r6,-0xA1234(r1,r0)
53 storw r5,0xA1234(r6,r5)
59 storw r5,-0xA1234(r6,r5)
72 storw r6,[r13]0xfffff(r1,r0)
95 storw $3,[r12]0xa7a(r6,r5)
96 storw $3,[r12]0xa7a(r7,r6)
103 storw $3,[r13]0xa7a(r6,r5)
104 storw $3,[r13]0xa7a(r7,r6)
108 storw $1,[r12]0x17a(r6,r5)
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/z8k/ |
| inout.d | 18 14: 3d6e in r14,@r6
26 24: 3de6 in r6,@r14
34 34: 3c66 inb rh6,@r6
46 50: 3bd8 0628 ind @r2,@r13,r6
50 60: 3b98 0368 ind @r6,@r9,r3
53 6c: 3b68 0f98 ind @r9,@r6,r15
62 90: 3ad8 0628 indb @r2,@r13,r6
66 a0: 3a98 0368 indb @r6,@r9,r3
69 ac: 3a68 0f98 indb @r9,@r6,r15
78 d0: 3bd8 0620 indr @r2,@r13,r6
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceRegList.h | 32 #define REGLIST7(ns, r0, r1, r2, r3, r4, r5, r6) \
35 ns::Reg_##r5, ns::Reg_##r6 \
|
| /external/valgrind/none/tests/amd64/ |
| sbbmisc.stdout.exp | 6 r6 = -69 -68
|
| /external/valgrind/none/tests/arm/ |
| v8memory_a.stdout.exp | 3 lda r6, [r10] with r10 = middle_of_block
14 94c87dfb r6 (xor, data intreg #3)
29 00000000 r6 (xor, data intreg #3)
44 00000000 r6 (xor, data intreg #3)
50 stl r6, [r10] with r10 = middle_of_block
61 00000000 r6 (xor, data intreg #3)
76 00000000 r6 (xor, data intreg #3)
91 00000000 r6 (xor, data intreg #3)
97 ldaex r6, [r10] with r10 = middle_of_block
108 9b7a3e28 r6 (xor, data intreg #3
[all...] |
| v8memory_t.stdout.exp | 3 lda r6, [r10] with r10 = middle_of_block
14 94c87dfb r6 (xor, data intreg #3)
29 00000000 r6 (xor, data intreg #3)
44 00000000 r6 (xor, data intreg #3)
50 stl r6, [r10] with r10 = middle_of_block
61 00000000 r6 (xor, data intreg #3)
76 00000000 r6 (xor, data intreg #3)
91 00000000 r6 (xor, data intreg #3)
97 ldaex r6, [r10] with r10 = middle_of_block
108 9b7a3e28 r6 (xor, data intreg #3
[all...] |
| /external/valgrind/none/tests/x86/ |
| sbbmisc.stdout.exp | 6 r6 = -69 -68
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| Deemph_32_opt.s | 38 LDRSH r6, [r0], #2 @load x_hi[0]
44 MOV r10, r6, LSL #16 @L_tmp = x_hi[0]<<16
50 LDRSH r6, [r0], #2 @load x_hi[1]
58 MOV r10, r6, LSL #16
69 LDRSH r6, [r0], #2 @load x_hi[]
72 MOV r10, r6, LSL #16
77 LDRSH r6, [r0], #2 @load x_hi[]
83 MOV r10, r6, LSL #16
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| Deemph_32_neon.s | 38 LDRSH r6, [r0], #2 @load x_hi[0]
44 MOV r10, r6, LSL #16 @L_tmp = x_hi[0]<<16
50 LDRSH r6, [r0], #2 @load x_hi[1]
58 MOV r10, r6, LSL #16
69 LDRSH r6, [r0], #2 @load x_hi[]
72 MOV r10, r6, LSL #16
77 LDRSH r6, [r0], #2 @load x_hi[]
83 MOV r10, r6, LSL #16
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| omxVCM4P10_FilterDeblockingLuma_HorEdge_I_s.S | 46 ADD r6,r0,r1
50 VLD1.8 {d6},[r6],r10
52 VLD1.8 {d4},[r6],r10
55 VLD1.8 {d9},[r6]
81 SUB r6,r0,r1,LSL #2
85 ADD r0,r6,#8
101 SUB r6,r0,r1,LSL #2
107 ADD r0,r6,#8
|
| /prebuilts/go/darwin-x86/src/runtime/cgo/ |
| gcc_s390x.S | 9 * Called from standard s390x C ABI, where r6-r13, r15, and f8-f15 are
14 /* save r6-r15 in the register save area of the calling function */
15 stmg %r6, %r15, 48(%r15)
50 lmg %r6, %r15, 48(%r15)
|
