| /prebuilts/go/linux-x86/src/runtime/cgo/ |
| gcc_s390x.S | 9 * Called from standard s390x C ABI, where r6-r13, r15, and f8-f15 are
14 /* save r6-r15 in the register save area of the calling function */
15 stmg %r6, %r15, 48(%r15)
50 lmg %r6, %r15, 48(%r15)
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arc/ |
| ld2.s | 4 ld r5,[r6,1]
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| ldst-offset0.s | 31 ldclpl p3, c5, [r6, #-0]
32 ldclpl p3, c5, [r6, #0]
60 stclpl p3, c5, [r6, #-0]
61 stclpl p3, c5, [r6, #0]
|
| mrs-msr-thumb-v7-m-bad.s | 9 msr xpsr_nncvq, r6
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cr16/ |
| add_test.s | 20 addb r5,r6
21 addb r6,r7
39 addcb r5,r6
40 addcb r6,r7
58 addcw r5,r6
59 addcw r6,r7
76 addw r5,r6
77 addw r6,r7
|
| jal_test.d | 11 2: 14 00 15 80 jal \(r6,r5\),\(r2,r1\)
|
| mov_test.s | 20 movb r5,r6
21 movb r6,r7
40 movw r5,r6
41 movw r6,r7
68 movxb r5,r6
76 movxw r5,(r6,r5)
84 movzb r5,r6
92 movzw r5,(r6,r5)
|
| push_test.s | 8 push $2,r6,RA
22 push $2,r6
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cris/ |
| rd-v32s-3.d | 11 [ ]+4:[ ]+3636[ ]+move r6,srs
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i860/ |
| dir-align01.s | 4 adds %r4,%r5,%r6
|
| dual02-err.s | 8 addu %r4,%r5,%r6
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/nios2/ |
| comments.s | 17 ori r6, r0, %lo(0x0) # r6 = 0x0
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/s390/ |
| zarch-machine.d | 10 .*: eb d6 65 b3 01 6a [ ]*asi 5555\(%r6\),-42
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/score/ |
| br.d | 36 50: 0f64 br! r6
37 52: 0f64 br! r6
45 70: 0f6c brl! r6
46 72: 0f6c brl! r6
|
| ls32ls16p.s | 32 \insn32 r6, [r6, 0x8 << \shift] #No transform
33 \insn32 r6, [r6, 0x8 << \shift] #No transform
|
| rD_rA_rB.s | 36 \insn32 r15, r15, r6 #No transform
57 \insn16 r6, r4 #No transform
58 \insn32 r6, r6, r4
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-crx/ |
| reloc-imm32.d | 12 11014000: f6 21 01 22 addd \$0x22014006, r6
|
| /external/v8/src/ppc/ |
| interface-descriptors-ppc.cc | 16 const Register default_stub_registers[] = {r3, r4, r5, r6, r7};
32 const Register LoadWithVectorDescriptor::VectorRegister() { return r6; }
41 const Register StoreWithVectorDescriptor::VectorRegister() { return r6; }
44 const Register StoreTransitionDescriptor::VectorRegister() { return r6; }
51 const Register ApiGetterDescriptor::CallbackRegister() { return r6; }
62 const Register GrowArrayElementsDescriptor::KeyRegister() { return r6; }
66 Register registers[] = {r4, r5, r6};
76 Register registers[] = {r6};
83 Register registers[] = {r6, r5, r4, r3};
90 Register registers[] = {r6, r5, r4}
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/ |
| parallel3.s | 5 r0 = VIT_MAX (r0, r6) (asr)|| [p0--] = P0;
14 r7 = R0 -|+ r6|| [p1++] = P0;
18 r6 = r3 -|- R4|| [p1+40] = P0; define
19 r7 = R5 -|- R6 (co)|| [p2] = P0;
22 R0 = R3 +|+ r6, R1 = R3 -|- R6 (ASL)|| [p2--] = P0;
23 R7 = R1 +|- R2, R6 = R1 -|+ R2 (S)|| [p2+36] = P0;
26 R5 = R0 + R1, R6 = R0 - R1|| [p3] = P0;
30 r3 = a0 + a1, r6 = a0 - a1 (s)|| [p3+28] = P0;
45 R6 = MAX (R0, R1) (V)|| [p5++] = P0
89 r6 = PACK (r1.H, r6.H)|| [p0++p2] = r0; define
[all...] |
| vector.s | 10 r0 = VIT_MAX (r0, r6) (asr);
25 r7 = R0 -|+ r6;
29 r6 = r3 -|- R4; define
30 r7 = R5 -|- R6 (co);
33 R0 = R3 +|+ r6, R1 = R3 -|- R6 (ASL);
34 R7 = R1 +|- R2, R6 = R1 -|+ R2 (S);
37 R5 = R0 + R1, R6 = R0 - R1;
41 r3 = a0 + a1, r6 = a0 - a1 (s);
65 R6 = MAX (R0, R1) (V)
122 r6 = PACK (r1.H, r6.H); define
[all...] |
| /external/llvm/test/MC/ARM/ |
| neon-vld-vst-align.s | 49 vld1.8 {d0}, [r4], r6
50 vld1.8 {d0}, [r4:16], r6
51 vld1.8 {d0}, [r4:32], r6
52 vld1.8 {d0}, [r4:64], r6
53 vld1.8 {d0}, [r4:128], r6
54 vld1.8 {d0}, [r4:256], r6
56 @ CHECK: vld1.8 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x07]
58 @ CHECK-ERRORS: vld1.8 {d0}, [r4:16], r6
61 @ CHECK-ERRORS: vld1.8 {d0}, [r4:32], r6
63 @ CHECK: vld1.8 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x07
[all...] |
| load-store-acquire-release-v8-thumb.s | 6 ldaexd r6, r7, [r8]
11 @ CHECK: ldaexd r6, r7, [r8] @ encoding: [0xd8,0xe8,0xff,0x67]
20 stlexd r6, r2, r3, [r8]
24 @ CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0xc8,0xe8,0xf6,0x23]
30 lda r5, [r6]
31 ldab r5, [r6]
33 @ CHECK: lda r5, [r6] @ encoding: [0xd6,0xe8,0xaf,0x5f]
34 @ CHECK: ldab r5, [r6] @ encoding: [0xd6,0xe8,0x8f,0x5f]
|
| load-store-acquire-release-v8.s | 6 ldaexd r6, r7, [r8]
11 @ CHECK: ldaexd r6, r7, [r8] @ encoding: [0x9f,0x6e,0xb8,0xe1]
20 stlexd r6, r2, r3, [r8]
24 @ CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0x92,0x6e,0xa8,0xe1]
30 lda r5, [r6]
31 ldab r5, [r6]
33 @ CHECK: lda r5, [r6] @ encoding: [0x9f,0x5c,0x96,0xe1]
34 @ CHECK: ldab r5, [r6] @ encoding: [0x9f,0x5c,0xd6,0xe1]
|
| /external/compiler-rt/lib/builtins/arm/ |
| sync-ops.h | 39 push {r4, r5, r6, lr} ; \
45 strexd r6, r4, r5, [r12] ; \
46 cmp r6, #0 ; \
49 pop {r4, r5, r6, pc}
|
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero.cc | 101 {{al, r0, r6, 0}, false, al, "al r0 r6 0", "al_r0_r6_0"},
109 {{al, r1, r6, 0}, false, al, "al r1 r6 0", "al_r1_r6_0"},
117 {{al, r2, r6, 0}, false, al, "al r2 r6 0", "al_r2_r6_0"},
125 {{al, r3, r6, 0}, false, al, "al r3 r6 0", "al_r3_r6_0"},
133 {{al, r4, r6, 0}, false, al, "al r4 r6 0", "al_r4_r6_0"}
[all...] |
