| /external/libyuv/files/source/ |
| scale_msa.cc | 70 v8u16 reg0, reg1, reg2, reg3; local
83 reg1 = __msa_hadd_u_h(vec1, vec1);
87 reg1 += reg3;
89 reg1 = (v8u16)__msa_srari_h((v8i16)reg1, 2);
90 dst0 = (v16u8)__msa_pckev_b((v16i8)reg1, (v16i8)reg0);
133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
158 reg1 = __msa_hadd_u_h(vec1, vec1);
162 reg5 = (v8u16)__msa_pckev_d((v2i64)reg3, (v2i64)reg1);
164 reg7 = (v8u16)__msa_pckod_d((v2i64)reg3, (v2i64)reg1);
296 v4u32 reg0, reg1, reg2, reg3; local
[all...] |
| /external/libvpx/libvpx/vpx_dsp/mips/ |
| txfm_macros_msa.h | 16 #define DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) \
27 ILVRL_H2_SW(reg1, reg0, s5_m, s4_m); \
28 ILVRL_H2_SW(reg0, reg1, s3_m, s2_m); \
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| i960-dis.c | 325 const char *reg1, *reg2, *reg3;
400 reg1 = reg_names[ (word1 >> 19) & 0x1f ]; /* MEMB only */
411 (*info->fprintf_func) (stream, ",%s", reg1);
420 (*info->fprintf_func)(stream, ",%s", reg1);
428 (*info->fprintf_func) (stream, "%s,", reg1);
434 (*info->fprintf_func) (stream, "%s,0x%x", reg1, (unsigned) offset);
324 const char *reg1, *reg2, *reg3; local
|
| mips-dis.c | 1311 unsigned int reg1, reg2; local
1534 unsigned int reg1, reg2; local
[all...] |
| /external/v8/src/interpreter/ |
| bytecode-register.h | 65 static bool AreContiguous(Register reg1, Register reg2,
|
| /external/vixl/src/aarch64/ |
| operands-aarch64.h | 474 bool AreAliased(const CPURegister& reg1,
487 // arguments. At least one argument (reg1) must be valid (not NoCPUReg).
488 bool AreSameSizeAndType(const CPURegister& reg1,
500 // arguments. At least one argument (reg1) must be valid (not NoVReg).
501 bool AreSameFormat(const VRegister& reg1,
509 // any subsequent arguments. At least one argument (reg1) must be valid
511 bool AreConsecutive(const VRegister& reg1,
520 explicit CPURegList(CPURegister reg1,
524 : list_(reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit()),
525 size_(reg1.GetSizeInBits())
[all...] |
| macro-assembler-aarch64.cc | [all...] |
| /external/aac/libFDK/src/ |
| fixpoint_math.cpp | 430 FIXP_DBL reg1, reg2, regtmp ; local
445 reg1 = invSqrtTab[ (INT)(val>>(DFRACT_BITS-1-(SQRT_BITS+1))) & SQRT_BITS_MASK ];
448 regtmp= fPow2Div2(reg1); /* a = Q^2 */
450 reg1 += (fMultDiv2(regtmp, reg1)<<4); /* Q = Q + Q*b */
455 reg1 = fMultDiv2(reg1, reg2) << 2;
460 return(reg1);
|
| /external/v8/src/compiler/mips/ |
| code-generator-mips.cc | 916 Register reg1 = kScratchReg; local
936 Register reg1 = kScratchReg; local
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64PBQPRegAlloc.cpp | 150 bool haveSameParity(unsigned reg1, unsigned reg2) {
151 assert(isFPReg(reg1) && "Expecting an FP register for reg1");
154 return isOdd(reg1) == isOdd(reg2);
|
| /external/vixl/src/aarch32/ |
| instructions-aarch32.h | 461 RegisterList(Register reg1, Register reg2)
462 : list_(RegisterToList(reg1) | RegisterToList(reg2)) {}
463 RegisterList(Register reg1, Register reg2, Register reg3)
464 : list_(RegisterToList(reg1) | RegisterToList(reg2) |
466 RegisterList(Register reg1, Register reg2, Register reg3, Register reg4)
467 : list_(RegisterToList(reg1) | RegisterToList(reg2) |
550 VRegisterList(VRegister reg1, VRegister reg2)
551 : list_(RegisterToList(reg1) | RegisterToList(reg2)) {}
552 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3)
553 : list_(RegisterToList(reg1) | RegisterToList(reg2)
[all...] |
| macro-assembler-aarch32.cc | 743 CPURegister reg1,
757 PushRegister(reg1);
763 (reg2.GetType() << 4) | reg1.GetType();
768 reg2.GetRegSizeInBytes() + reg1.GetRegSizeInBytes();
782 if (reg1.GetType() == CPURegister::kRRegister) {
783 available_registers.Remove(Register(reg1.GetCode()));
805 PushRegister(reg1);
812 PreparePrintfArgument(reg1, &core_count, &vfp_count, &printf_type);
[all...] |
| /external/vixl/test/aarch64/ |
| test-utils-aarch64.h | 214 const Register& reg1);
|
| test-utils-aarch64.cc | 197 const Register& reg1) {
198 VIXL_ASSERT(reg0.Is64Bits() && reg1.Is64Bits());
200 int64_t result = core->xreg(reg1.GetCode());
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| RenderMachineFunction.cpp | 173 unsigned reg1, reg2; local
174 if ((iss >> reg1 >> std::ws)) {
176 intervalNumsToRender.insert(std::make_pair(reg1, reg1 + 1));
181 intervalNumsToRender.insert(std::make_pair(reg1, reg2 + 1));
[all...] |
| /external/v8/src/arm/ |
| macro-assembler-arm.cc | 215 void MacroAssembler::Swap(Register reg1,
220 eor(reg1, reg1, Operand(reg2), LeaveCC, cond);
221 eor(reg2, reg2, Operand(reg1), LeaveCC, cond);
222 eor(reg1, reg1, Operand(reg2), LeaveCC, cond);
224 mov(scratch, reg1, LeaveCC, cond);
225 mov(reg1, reg2, LeaveCC, cond);
[all...] |
| /art/runtime/arch/arm64/ |
| quick_entrypoints_arm64.S | 54 .macro SAVE_TWO_REGS reg1, reg2, offset
55 stp \reg1, \reg2, [sp, #(\offset)]
56 .cfi_rel_offset \reg1, (\offset)
60 .macro RESTORE_TWO_REGS reg1, reg2, offset
61 ldp \reg1, \reg2, [sp, #(\offset)]
62 .cfi_restore \reg1
66 .macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment
67 stp \reg1, \reg2, [sp, #-(\frame_adjustment)]!
69 .cfi_rel_offset \reg1, 0
73 .macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustmen
[all...] |
| /external/mesa3d/src/gallium/drivers/ilo/shader/ |
| toy_legalize_ra.c | 82 const int *reg1 = elem1; local
86 return (*reg2 - *reg1);
|
| /external/v8/src/full-codegen/ |
| full-codegen.h | 303 void PushOperands(Register reg1, Register reg2);
304 void PushOperands(Register reg1, Register reg2, Register reg3);
305 void PushOperands(Register reg1, Register reg2, Register reg3, Register reg4);
306 void PopOperands(Register reg1, Register reg2);
[all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-ia64.c | 3373 unsigned reg1, reg2; local
3778 int reg1, val; local
6114 int reg1, reg2; local
[all...] |
| tc-avr.c | 1144 unsigned int reg1 = 0; local
[all...] |
| /external/syslinux/gpxe/src/drivers/net/ |
| sky2.c | 596 u32 reg1; local
599 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
600 reg1 &= ~phy_power[port];
603 reg1 |= coma_mode[port];
605 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
617 u32 reg1; local
662 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
663 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
664 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
[all...] |
| /external/v8/src/arm64/ |
| assembler-arm64.cc | 212 Register GetAllocatableRegisterThatIsNotOneOf(Register reg1, Register reg2,
214 CPURegList regs(reg1, reg2, reg3, reg4);
227 bool AreAliased(const CPURegister& reg1, const CPURegister& reg2,
237 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
264 bool AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2,
268 DCHECK(reg1.IsValid());
270 match &= !reg2.IsValid() || reg2.IsSameSizeAndType(reg1);
271 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
272 match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1);
273 match &= !reg5.IsValid() || reg5.IsSameSizeAndType(reg1);
[all...] |
| assembler-arm64.h | 347 Register GetAllocatableRegisterThatIsNotOneOf(Register reg1,
355 bool AreAliased(const CPURegister& reg1,
367 // arguments. At least one argument (reg1) must be valid (not NoCPUReg).
368 bool AreSameSizeAndType(const CPURegister& reg1,
387 explicit CPURegList(CPURegister reg1,
391 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
392 size_(reg1.SizeInBits()), type_(reg1.type()) {
393 DCHECK(AreSameSizeAndType(reg1, reg2, reg3, reg4));
[all...] |
| /art/compiler/utils/x86_64/ |
| assembler_x86_64.h | 615 void cmpl(CpuRegister reg0, CpuRegister reg1);
620 void cmpq(CpuRegister reg0, CpuRegister reg1);
625 void testl(CpuRegister reg1, CpuRegister reg2);
629 void testq(CpuRegister reg1, CpuRegister reg2);
[all...] |
