| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/x86/x86asm/ |
| gnu.go | 29 _, reg2 := inst.Args[1].(Reg)
30 if reg1 && reg2 && (inst.Opcode>>24 == 0xDC || inst.Opcode>>24 == 0xDE) {
|
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/x86/x86asm/ |
| gnu.go | 29 _, reg2 := inst.Args[1].(Reg)
30 if reg1 && reg2 && (inst.Opcode>>24 == 0xDC || inst.Opcode>>24 == 0xDE) {
|
| /external/v8/src/s390/ |
| macro-assembler-s390.cc | [all...] |
| /art/compiler/utils/x86_64/ |
| assembler_x86_64.h | 625 void testl(CpuRegister reg1, CpuRegister reg2);
629 void testq(CpuRegister reg1, CpuRegister reg2);
[all...] |
| assembler_x86_64.cc | [all...] |
| /art/compiler/utils/mips/ |
| assembler_mips_test.cc | 259 DriverStr(RepeatRRR(&mips::MipsAssembler::Addu, "addu ${reg1}, ${reg2}, ${reg3}"), "Addu");
263 DriverStr(RepeatRRIb(&mips::MipsAssembler::Addiu, -16, "addiu ${reg1}, ${reg2}, {imm}"), "Addiu");
267 DriverStr(RepeatRRR(&mips::MipsAssembler::Subu, "subu ${reg1}, ${reg2}, ${reg3}"), "Subu");
271 DriverStr(RepeatRR(&mips::MipsAssembler::MultR2, "mult ${reg1}, ${reg2}"), "MultR2");
275 DriverStr(RepeatRR(&mips::MipsAssembler::MultuR2, "multu ${reg1}, ${reg2}"), "MultuR2");
279 DriverStr(RepeatRR(&mips::MipsAssembler::DivR2, "div $zero, ${reg1}, ${reg2}"), "DivR2Basic");
283 DriverStr(RepeatRR(&mips::MipsAssembler::DivuR2, "divu $zero, ${reg1}, ${reg2}"), "DivuR2Basic");
287 DriverStr(RepeatRRR(&mips::MipsAssembler::MulR2, "mul ${reg1}, ${reg2}, ${reg3}"), "MulR2");
291 DriverStr(RepeatRRR(&mips::MipsAssembler::DivR2, "div $zero, ${reg2}, ${reg3}\nmflo ${reg1}"),
296 DriverStr(RepeatRRR(&mips::MipsAssembler::ModR2, "div $zero, ${reg2}, ${reg3}\nmfhi ${reg1}")
[all...] |
| /art/runtime/arch/mips/ |
| quick_entrypoints_mips.S | 868 .macro LOAD_LONG_TO_REG reg1, reg2, next_arg, index_reg, next_index, label
870 lw $\reg2, -4($\next_arg)
885 .macro LOAD_DOUBLE_TO_REG reg1, reg2, next_arg, index_reg, tmp, label
887 LDu $\reg1, $\reg2, -8, $\next_arg, $\tmp # next_arg points to argument after the current one
895 .macro LOAD_DOUBLE_TO_REG reg1, reg2, next_arg, index_reg, tmp, label
896 LDu $\reg1, $\reg2, -8, $\next_arg, $\tmp # next_arg points to argument after the current one
[all...] |
| /external/elfutils/tests/ |
| run-addrcfi.sh | 35 integer reg2 (%edx): undefined
82 integer reg2 (%edx): undefined
134 integer reg2 (%rcx): undefined
200 integer reg2 (%rcx): undefined
304 integer reg2 (r2): same_value
[all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.h | 739 #define DECLARE_FUNCTION(FN, REGTYPE, REG, REG2, OP) \
740 void FN(const REGTYPE REG, const REGTYPE REG2, const MemOperand& addr);
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-opc.c | 2234 const int reg2 = (first_reg + 2) & 0x1f; local
[all...] |
| /art/compiler/utils/x86/ |
| assembler_x86.h | 593 void testl(Register reg1, Register reg2);
|
| /external/elfutils/libdw/ |
| known-dwarf.h | 510 DWARF_ONE_KNOWN_DW_OP (reg2, DW_OP_reg2) \
[all...] |
| /external/libyuv/files/include/libyuv/ |
| row.h | 596 #define VMEMOPREG(opcode, offset, base, index, scale, reg1, reg2) \
599 " (%%r15,%%r14),%%" #reg1 ",%%" #reg2 "\n" BUNDLEUNLOCK
621 #define VMEMOPREG(opcode, offset, base, index, scale, reg1, reg2) \
623 ",%%" #reg2 "\n"
[all...] |
| /external/v8/src/full-codegen/arm/ |
| full-codegen-arm.cc | [all...] |
| /external/v8/src/ia32/ |
| macro-assembler-ia32.cc | [all...] |
| macro-assembler-ia32.h | 48 bool AreAliased(Register reg1, Register reg2, Register reg3 = no_reg,
[all...] |
| /external/v8/src/x87/ |
| macro-assembler-x87.cc | [all...] |
| macro-assembler-x87.h | 51 bool AreAliased(Register reg1, Register reg2, Register reg3 = no_reg,
[all...] |
| /external/valgrind/VEX/priv/ |
| host_s390_isel.c | 3386 HReg reg1, reg2; local
[all...] |
| /external/libpcap/ |
| gencode.c | [all...] |
| /external/boringssl/src/crypto/cipher_extra/asm/ |
| aes128gcmsiv-x86_64.pl | 574 my ($reg, $reg2, $auxReg) = @_;
580 vpxor $reg2, $reg, $reg
[all...] |
| /external/v8/src/x64/ |
| macro-assembler-x64.cc | [all...] |
| macro-assembler-x64.h | 69 Register reg2,
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerX86BaseImpl.h | [all...] |
| /external/v8/src/crankshaft/x87/ |
| lithium-codegen-x87.cc | 409 void LCodeGen::X87LoadForUsage(X87Register reg1, X87Register reg2) {
411 DCHECK(x87_stack_.Contains(reg2));
412 if (reg1.is(reg2) && x87_stack_.depth() == 1) {
419 x87_stack_.Fxch(reg2);
[all...] |
