| /hardware/intel/common/libva/va/ |
| va_tpi.h | 57 unsigned int tiling; /* the memory is tiling or not */ member in struct:_VASurfaceAttributeTPI
|
| /hardware/intel/img/hwcomposer/merrifield/ips/common/ |
| VideoPayloadBuffer.h | 35 int tiling; member in struct:android::intel::VideoPayloadBuffer
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| /hardware/intel/img/hwcomposer/moorefield_hdmi/ips/common/ |
| VideoPayloadBuffer.h | 35 int tiling; member in struct:android::intel::VideoPayloadBuffer
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| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_winsys.h | 160 * the tiling mode provide in *tiling. If tiling is no possible, *tiling will
167 enum i915_winsys_buffer_tile *tiling,
180 enum i915_winsys_buffer_tile *tiling,
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| i915_state_static.c | 79 buf_3d_tiling_bits(enum i915_winsys_buffer_tile tiling)
83 switch (tiling) {
110 buf_3d_tiling_bits(tex->tiling);
135 buf_3d_tiling_bits(tex->tiling);
218 if (is->is_i945 && tex->tiling != I915_TILE_NONE
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| i915_resource.h | 69 /* tiling flags */
70 enum i915_winsys_buffer_tile tiling; member in struct:i915_texture
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| /external/mesa3d/src/intel/vulkan/ |
| anv_gem_stubs.c | 98 uint32_t gem_handle, uint32_t stride, uint32_t tiling)
124 anv_gem_get_bit6_swizzle(int fd, uint32_t tiling)
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| anv_gem.c | 176 uint32_t gem_handle, uint32_t stride, uint32_t tiling)
186 .tiling_mode = tiling,
214 anv_gem_get_bit6_swizzle(int fd, uint32_t tiling)
236 .tiling_mode = tiling,
237 .stride = tiling == I915_TILING_X ? 512 : 128,
244 assert(!"Failed to set BO tiling");
253 assert(!"Failed to get BO tiling");
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| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| intel_regions.h | 69 uint32_t tiling; /**< Which tiling mode the region is in */ member in struct:intel_region
79 uint32_t tiling,
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| intel_clear.c | 128 * the tiling bits to determine how to clear. */
137 if (stencilRegion->tiling == I915_TILING_Y ||
157 if (irb->tiling == I915_TILING_Y || tri_mask & BUFFER_BIT_STENCIL)
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| intel_mipmap_tree.h | 253 uint32_t tiling);
298 uint32_t tiling,
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| /external/mesa3d/src/intel/isl/ |
| isl_storage_image.c | 246 switch (surf->tiling) {
253 param->tiling[0] = isl_log2u(512 / cpp);
254 param->tiling[1] = isl_log2u(8);
269 * one arranged in X-major order just like is the case for X-tiling.
271 param->tiling[0] = isl_log2u(16 / cpp);
272 param->tiling[1] = isl_log2u(32);
284 assert(!"Unhandled storage image tiling");
289 * brw_fs_surface_builder.cpp) handles this as a sort of tiling with
292 param->tiling[2] = (ISL_DEV_GEN(dev) < 9 && surf->dim == ISL_SURF_DIM_3D ?
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| /external/deqp/external/vulkancts/modules/vulkan/ycbcr/ |
| vktYCbCrFormatTests.cpp | 78 VkImageTiling tiling,
92 tiling,
230 VkImageTiling tiling; member in struct:vkt::ycbcr::__anon16855::TestParameters
243 , tiling (tiling_)
252 , tiling (VK_IMAGE_TILING_OPTIMAL)
277 checkImageSupport(context, params.format, params.flags, params.tiling);
305 const VkImageTiling tiling = params.tiling; local
308 const Unique<VkImage> image (createTestImage(vkd, device, format, size, createFlags, tiling, mappedMemory ? VK_IMAGE_LAYOUT_PREINITIALIZED : VK_IMAGE_LAYOUT_UNDEFINED));
507 const VkImageTiling tiling = tilings[tilingNdx].value local
[all...] |
| /external/mesa3d/src/gallium/drivers/vc4/ |
| vc4_cl_dump.c | 114 const char *tiling = "???"; local
117 tiling = "linear";
120 tiling = "T";
123 tiling = "LT";
142 buffer, tiling);
315 const char *tiling = "???"; local
318 tiling = "linear";
321 tiling = "T";
324 tiling = "LT";
331 format, tiling,
[all...] |
| /external/mesa3d/src/gallium/winsys/intel/drm/ |
| intel_drm_winsys.c | 95 uint32_t tiling = I915_TILING_X, swizzle; local
99 "address swizzling test", 64, 64, 4, &tiling, &pitch, 0);
101 drm_intel_bo_get_tiling(bo, &tiling, &swizzle);
309 enum intel_tiling_mode *tiling,
350 *tiling = real_tiling;
359 enum intel_tiling_mode tiling,
490 enum intel_tiling_mode tiling,
493 uint32_t real_tiling = tiling;
496 switch (tiling) {
510 if (err || real_tiling != tiling) {
[all...] |
| /external/libdrm/tegra/ |
| tegra.c | 341 struct drm_tegra_bo_tiling *tiling)
358 if (tiling) {
359 tiling->mode = args.mode;
360 tiling->value = args.value;
367 const struct drm_tegra_bo_tiling *tiling)
378 args.mode = tiling->mode;
379 args.value = tiling->value;
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| /external/mesa3d/src/gallium/winsys/i915/drm/ |
| i915_drm_buffer.c | 57 enum i915_winsys_buffer_tile *tiling,
63 uint32_t tiling_mode = *tiling;
81 *tiling = tiling_mode;
94 enum i915_winsys_buffer_tile *tiling,
129 *tiling = tile;
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| /external/mesa3d/src/gallium/drivers/ilo/ |
| ilo_blitter_blt.c | 252 /* no W-tiling nor separate stencil support */
253 if (dst_tex->image.tiling == GEN8_TILING_W || dst_tex->separate_s8)
265 dst.tiling = dst_tex->image.tiling;
269 dst_tex->vma.bo, dst_tex->image.tiling, NULL, GEN6_TILING_NONE);
312 /* no W-tiling nor separate stencil support */
313 if (dst_tex->image.tiling == GEN8_TILING_W || dst_tex->separate_s8 ||
314 src_tex->image.tiling == GEN8_TILING_W || src_tex->separate_s8)
354 dst.tiling = dst_tex->image.tiling;
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| intel_tex_subimage.c | 66 * of version 21) renders each page as a tiling of 256x256 GL_BGRA textures.
133 (image->mt->tiling != I915_TILING_X &&
134 image->mt->tiling != I915_TILING_Y)) {
163 "mesa_format=0x%x tiling=%d "
167 format, type, texImage->TexFormat, image->mt->tiling,
184 image->mt->tiling,
|
| intel_mipmap_tree.h | 374 uint32_t tiling; member in struct:intel_mipmap_tree
671 unsigned tiling);
784 get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling,
809 intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
813 intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp,
[all...] |
| /external/deqp/external/vulkancts/framework/vulkan/ |
| vkQueryUtil.cpp | 110 VkImageFormatProperties getPhysicalDeviceImageFormatProperties (const InstanceInterface& vk, VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags)
116 VK_CHECK(vk.getPhysicalDeviceImageFormatProperties(physicalDevice, format, type, tiling, usage, flags, &properties));
120 std::vector<VkSparseImageFormatProperties> getPhysicalDeviceSparseImageFormatProperties(const InstanceInterface& vk, VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkSampleCountFlagBits samples, VkImageUsageFlags usage, VkImageTiling tiling)
125 vk.getPhysicalDeviceSparseImageFormatProperties(physicalDevice, format, type, samples, usage, tiling, &numProp, DE_NULL);
130 vk.getPhysicalDeviceSparseImageFormatProperties(physicalDevice, format, type, samples, usage, tiling, &numProp, &properties[0]);
|
| /external/mesa3d/src/gallium/drivers/ilo/core/ |
| ilo_image.c | 48 enum gen_surface_tiling tiling; member in struct:ilo_image_layout
171 * "The Depth Buffer, if tiled, must use Y-Major tiling."
272 * X-tiling has the property that vertically adjacent pixels are usually in
277 * Y-tiling is similar, where vertically adjacent pixels are usually in the
330 enum gen_surface_tiling tiling)
372 tiling == GEN6_TILING_NONE ||
445 enum gen_surface_tiling tiling,
522 (tiling == GEN6_TILING_Y && info->bind_surface_dp_render));
554 layout->tiling = image_get_gen6_tiling(dev, info, layout->valid_tilings);
559 image_get_gen7_mcs_enable(dev, info, layout->tiling))
[all...] |
| ilo_image.h | 164 enum gen_surface_tiling tiling; member in struct:ilo_image
242 switch (img->tiling) {
260 assert(!"unknown tiling");
|
| /external/mesa3d/docs/specs/ |
| WL_create_wayland_buffer_from_image.spec | 82 format or tiling mode or that the buffer is in memory that is inaccessible
88 this include for example unsupported tiling modes?
93 unsupported tiling modes, inaccessible memory or an unsupported pixel
|
| /external/skia/src/gpu/vk/ |
| GrVkImage.cpp | 132 void GrVkImage::setNewResource(VkImage image, const GrVkAlloc& alloc, VkImageTiling tiling) {
133 fResource = new Resource(image, alloc, tiling);
|
