| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips64.s | 12 dclz $3, $4
|
| mips64.d | 11 0+0004 <[^>]*> 70831824 dclz v1,a0
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| micromips@mips64.d | 12 [0-9a-f]+ <[^>]*> 5864 5b3c dclz v1,a0
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| mipsr6@mips64.d | 12 0+0004 <[^>]*> 00801852 dclz v1,a0
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| r6-64.s | 14 dclz $2,$3
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| vr5500.s | 68 dclz $3,$4
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| r6-64-n32.d | 21 0+0028 <[^>]*> 00601052 dclz v0,v1
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| r6-64-n64.d | 21 0+0028 <[^>]*> 00601052 dclz v0,v1
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| vr5500.d | 46 0+00098 <stuff\+0x98> dclz v1,a0
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| set-arch.s | 300 dclz $3, $4
482 dclz $3,$4
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips64.s | 9 dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/CodeGen/Mips/ |
| countleading.ll | 54 ; MIPS4-NOT: dclz
65 ; MIPS64-GT-R1: dclz $2, $4
66 ; MICROMIPS64: dclz $2, $4
|
| mips64instrs.ll | 189 ; The MIPS4 version is too long to reasonably test. At least check we don't get dclz
190 ; MIPS4-NOT: dclz
192 ; HAS-DCLO: dclz $2, $4
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| /bionic/libc/arch-mips/string/ |
| strlen.c | 47 "dclz %1, %0 \n\t"
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| strnlen.c | 47 "dclz %1, %0 \n\t"
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| memchr.c | 54 "dclz %1, %0 \n\t"
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64.s | 12 dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64r2.s | 11 dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64.s | 11 dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64r2.s | 11 dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/valgrind/none/tests/mips64/ |
| arithmetic_instruction.c | 8 DADDIU, DADDU, DCLO, DCLZ,
127 case DCLZ:
129 TEST3("dclz $t0, $t1", reg_val1[i], t0, t1);
130 TEST3("dclz $v0, $v1", reg_val2[i], v0, v1);
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| mips64instrs.ll | 123 ; CHECK: dclz $2, $4
|
| /external/llvm/lib/Target/Mips/ |
| Mips64r6InstrInfo.td | 15 // Reencoded: dclo, dclz
63 class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd, II_DCLZ>;
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| MicroMips64r6InstrInfo.td | 59 class DCLZ_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dclz", 0b0101101100>;
145 string AsmString = !strconcat("dclz", "\t$rt, $rs");
149 string BaseOpcode = "dclz";
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| Mips64InstrInfo.td | 182 def DCLZ : CountLeading64<0x24, "dclz",
|
