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  /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/OmapDmaLib/
OmapDmaLib.c 29 @param Dma4 Pointer to structure used to initialize DMA registers for the Channel
40 IN OMAP_DMA4 *DMA4
61 RegVal = ((RegVal & ~ 0x3) | DMA4->DataType );
62 RegVal = ((RegVal & ~(0x3 << 7)) | (DMA4->ReadPortAccessType << 7));
63 RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessType << 14));
64 RegVal = ((RegVal & ~(0x1 << 21)) | (DMA4->SourceEndiansim << 21));
65 RegVal = ((RegVal & ~(0x1 << 19)) | (DMA4->DestinationEndianism << 19));
66 RegVal = ((RegVal & ~(0x3 << 16)) | (DMA4->WriteMode << 16));
67 RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->SourcePacked << 6));
68 RegVal = ((RegVal & ~(0x1 << 13)) | (DMA4->DestinationPacked << 13));
    [all...]
  /device/linaro/bootloader/edk2/Omap35xxPkg/Library/OmapDmaLib/
OmapDmaLib.c 29 @param Dma4 Pointer to structure used to initialize DMA registers for the Channel
40 IN OMAP_DMA4 *DMA4
61 RegVal = ((RegVal & ~ 0x3) | DMA4->DataType );
62 RegVal = ((RegVal & ~(0x3 << 7)) | (DMA4->ReadPortAccessType << 7));
63 RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessType << 14));
64 RegVal = ((RegVal & ~(0x1 << 21)) | (DMA4->SourceEndiansim << 21));
65 RegVal = ((RegVal & ~(0x1 << 19)) | (DMA4->DestinationEndianism << 19));
66 RegVal = ((RegVal & ~(0x3 << 16)) | (DMA4->WriteMode << 16));
67 RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->SourcePacked << 6));
68 RegVal = ((RegVal & ~(0x1 << 13)) | (DMA4->DestinationPacked << 13));
    [all...]
  /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/MMCHSDxe/
MMCHS.c 748 OMAP_DMA4 Dma4;
764 Dma4.DataType = 2; // DMA4_CSDPi[1:0] 32-bit elements from MMCHS_DATA
766 Dma4.SourceEndiansim = 0; // DMA4_CSDPi[21]
768 Dma4.DestinationEndianism = 0; // DMA4_CSDPi[19]
770 Dma4.SourcePacked = 0; // DMA4_CSDPi[6]
772 Dma4.DestinationPacked = 0; // DMA4_CSDPi[13]
774 Dma4.NumberOfElementPerFrame = This->Media->BlockSize/4; // DMA4_CENi (TRM 4K is optimum value)
776 Dma4.NumberOfFramePerTransferBlock = BlockCount; // DMA4_CFNi
778 Dma4.ReadPriority = 0; // DMA4_CCRi[6] Low priority read
780 Dma4.WritePriority = 0; // DMA4_CCRi[23] Prefetech disabled
    [all...]
  /device/linaro/bootloader/edk2/Omap35xxPkg/MMCHSDxe/
MMCHS.c 748 OMAP_DMA4 Dma4;
764 Dma4.DataType = 2; // DMA4_CSDPi[1:0] 32-bit elements from MMCHS_DATA
766 Dma4.SourceEndiansim = 0; // DMA4_CSDPi[21]
768 Dma4.DestinationEndianism = 0; // DMA4_CSDPi[19]
770 Dma4.SourcePacked = 0; // DMA4_CSDPi[6]
772 Dma4.DestinationPacked = 0; // DMA4_CSDPi[13]
774 Dma4.NumberOfElementPerFrame = This->Media->BlockSize/4; // DMA4_CENi (TRM 4K is optimum value)
776 Dma4.NumberOfFramePerTransferBlock = BlockCount; // DMA4_CFNi
778 Dma4.ReadPriority = 0; // DMA4_CCRi[6] Low priority read
780 Dma4.WritePriority = 0; // DMA4_CCRi[23] Prefetech disabled
    [all...]
  /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Library/
OmapDmaLib.h 53 @param Dma4 Pointer to structure used to initialize DMA registers for the Channel
64 IN OMAP_DMA4 *Dma4
  /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Library/
OmapDmaLib.h 53 @param Dma4 Pointer to structure used to initialize DMA registers for the Channel
64 IN OMAP_DMA4 *Dma4

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