| /external/llvm/test/MC/AArch64/ |
| neon-simd-ldst-one-elem.s | 63 ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]
64 ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]
65 ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]
66 ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
67 ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
68 ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]
69 ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
70 ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp]
71 // CHECK: ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0xe0,0x60,0x4d]
72 // CHECK: ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0xe5,0x60,0x4d
[all...] |
| arm64-simd-ldst.s | 1012 ld4r: label
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| neon-vfp-reglist.d | 165 274: 0d60e000 ld4r {v0.8b-v3.8b}, \[x0\]
169 284: 4d60e000 ld4r {v0.16b-v3.16b}, \[x0\]
173 294: 0d60e400 ld4r {v0.4h-v3.4h}, \[x0\]
177 2a4: 4d60e400 ld4r {v0.8h-v3.8h}, \[x0\]
181 2b4: 0d60e800 ld4r {v0.2s-v3.2s}, \[x0\]
185 2c4: 4d60e800 ld4r {v0.4s-v3.4s}, \[x0\]
189 2d4: 0d60ec00 ld4r {v0.1d-v3.1d}, \[x0\]
193 2e4: 4d60ec00 ld4r {v0.2d-v3.2d}, \[x0\]
|
| neon-vfp-reglist-post.d | 227 36c: 0dffe000 ld4r {v0.8b-v3.8b}, \[x0\], #4
231 37c: 4dffe000 ld4r {v0.16b-v3.16b}, \[x0\], #4
243 3ac: 0dffe400 ld4r {v0.4h-v3.4h}, \[x0\], #8
247 3bc: 4dffe400 ld4r {v0.8h-v3.8h}, \[x0\], #8
259 3ec: 0dffe800 ld4r {v0.2s-v3.2s}, \[x0\], #16
263 3fc: 4dffe800 ld4r {v0.4s-v3.4s}, \[x0\], #16
275 42c: 0dffec00 ld4r {v0.1d-v3.1d}, \[x0\], #32
279 43c: 4dffec00 ld4r {v0.2d-v3.2d}, \[x0\], #32
303 49c: 0de7e000 ld4r {v0.8b-v3.8b}, \[x0\], x7
307 4ac: 4de7e000 ld4r {v0.16b-v3.16b}, \[x0\], x
[all...] |
| illegal.l | 84 [^:]*:124: Error: .*`ld4r {v1.4s},\[x3\]'
89 [^:]*:130: Error: .*`ld4r {v1.4s},\[x3\],x4'
94 [^:]*:136: Error: .*`ld4r {v1.4s,v2.4s,v3.4s,v4.4s},\[x3\],#32'
295 [^:]*:322: Error: .*`ld4r {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#8'
298 [^:]*:322: Error: .*`ld4r {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#8'
307 [^:]*:337: Error: .*`ld4r {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#16'
310 [^:]*:337: Error: .*`ld4r {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#16'
319 [^:]*:352: Error: .*`ld4r {v0.1d,v2.1d,v4.1d,v6.1d},\[x0\],#32'
322 [^:]*:352: Error: .*`ld4r {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#32'
348 [^:]*:373: Error: .*`ld4r {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7
[all...] |
| illegal.s | 124 ld4r {v1.4s}, [x3]
130 ld4r {v1.4s}, [x3], x4
136 ld4r {v1.4s, v2.4s, v3.4s, v4.4s}, [x3], #32
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 494 { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
495 { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
496 { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
497 { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
498 { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
499 { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
500 { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
501 { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
502 { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
503 { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 }
[all...] |
| /external/valgrind/none/tests/arm64/ |
| memory.c | [all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-ld1.ll | 575 ; CHECK: ld4r.8b { v0, v1, v2, v3 }, [x0]
577 %tmp2 = call %struct.__neon_int8x8x4_t @llvm.aarch64.neon.ld4r.v8i8.p0i8(i8* %A)
583 declare %struct.__neon_int8x8x4_t @llvm.aarch64.neon.ld4r.v8i8.p0i8(i8*) nounwind readonly
606 ; CHECK: ld4r.16b { v0, v1, v2, v3 }, [x0]
608 %tmp2 = call %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4r.v16i8.p0i8(i8* %A)
614 declare %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4r.v16i8.p0i8(i8*) nounwind readonly
637 ; CHECK: ld4r.4h { v0, v1, v2, v3 }, [x0]
639 %tmp2 = call %struct.__neon_int16x4x4_t @llvm.aarch64.neon.ld4r.v4i16.p0i16(i16* %A)
645 declare %struct.__neon_int16x4x4_t @llvm.aarch64.neon.ld4r.v4i16.p0i16(i16*) nounwind readonly
668 ; CHECK: ld4r.8h { v0, v1, v2, v3 }, [x0
[all...] |
| arm64-indexed-vector-ldst.ll | [all...] |
| fp16-vector-load-store.ll | 226 declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4r.v4f16.p0f16(half*)
229 declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4r.v8f16.p0f16(half*)
252 ; CHECK: ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x0]
254 %0 = tail call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4r.v4f16.p0f16(half* %a)
279 ; CHECK: ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x0]
281 %0 = tail call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4r.v8f16.p0f16(half* %a)
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | [all...] |
| /external/vixl/test/aarch64/ |
| test-trace-aarch64.cc | [all...] |
| test-disasm-aarch64.cc | [all...] |
| test-assembler-aarch64.cc | [all...] |
| /external/vixl/test/test-trace-reference/ |
| log-disasm | [all...] |
| log-disasm-colour | [all...] |
| log-all | [all...] |
| /external/clang/test/CodeGen/ |
| aarch64-neon-ldst-one.c | [all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_Resize.S | 490 ld4r {v12.8h,v13.8h,v14.8h,v15.8h}, [x14]
534 ld4r {v12.4s,v13.4s,v14.4s,v15.4s}, [x14]
569 ld4r {v12.4s,v13.4s,v14.4s,v15.4s}, [x14]
|
| rsCpuIntrinsics_advsimd_3DLUT.S | 218 4: ld4r {v0.8b-v3.8b}, [x1]
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64SchedKryoDetails.td | [all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-dis-2.c | [all...] |
| /external/vixl/doc/aarch64/ |
| supported-instructions-aarch64.md | [all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.h | [all...] |
