| /art/runtime/interpreter/mterp/arm/ |
| op_iget_boolean_quick.S | 1 %include "arm/op_iget_quick.S" { "load":"ldrb" }
|
| op_aget_boolean.S | 1 %include "arm/op_aget.S" { "load":"ldrb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" }
|
| /art/runtime/interpreter/mterp/arm64/ |
| op_iget_boolean_quick.S | 1 %include "arm64/op_iget_quick.S" { "load":"ldrb" }
|
| op_aget_boolean.S | 1 %include "arm64/op_aget.S" { "load":"ldrb", "shift":"0", "data_offset":"MIRROR_BOOLEAN_ARRAY_DATA_OFFSET" }
|
| /external/vixl/test/aarch32/traces/ |
| assembler-cond-rd-memop-immediate-8192-a32-ldrb.h | 38 0x00, 0xd0, 0xd0, 0x55 // ldrb pl r13 r0 plus 0 Offset
41 0x00, 0x50, 0xd3, 0xa5 // ldrb ge r5 r3 plus 0 Offset
44 0x00, 0x00, 0xd4, 0x35 // ldrb cc r0 r4 plus 0 Offset
47 0x00, 0x00, 0xd0, 0xa5 // ldrb ge r0 r0 plus 0 Offset
50 0x00, 0xc0, 0xd3, 0x05 // ldrb eq r12 r3 plus 0 Offset
53 0x00, 0x40, 0xdd, 0xe5 // ldrb al r4 r13 plus 0 Offset
56 0x00, 0x80, 0xd2, 0x45 // ldrb mi r8 r2 plus 0 Offset
59 0x00, 0x60, 0xd9, 0x45 // ldrb mi r6 r9 plus 0 Offset
62 0x00, 0xd0, 0xdb, 0xc5 // ldrb gt r13 r11 plus 0 Offset
65 0x00, 0x00, 0xd7, 0x25 // ldrb cs r0 r7 plus 0 Offse
[all...] |
| assembler-cond-rd-memop-rs-a32-ldrb.h | 38 0x06, 0x80, 0xdb, 0x57 // ldrb pl r8 r11 plus r6 Offset
41 0x05, 0x40, 0xd8, 0xd7 // ldrb le r4 r8 plus r5 Offset
44 0x0e, 0x20, 0xd6, 0x67 // ldrb vs r2 r6 plus r14 Offset
47 0x08, 0x10, 0xd7, 0x97 // ldrb ls r1 r7 plus r8 Offset
50 0x0e, 0xe0, 0xd6, 0xa7 // ldrb ge r14 r6 plus r14 Offset
53 0x07, 0x70, 0xd0, 0x27 // ldrb cs r7 r0 plus r7 Offset
56 0x09, 0xb0, 0xd0, 0xa7 // ldrb ge r11 r0 plus r9 Offset
59 0x04, 0x70, 0xda, 0x07 // ldrb eq r7 r10 plus r4 Offset
62 0x03, 0x90, 0xd2, 0xe7 // ldrb al r9 r2 plus r3 Offset
65 0x06, 0xb0, 0xda, 0x37 // ldrb cc r11 r10 plus r6 Offse
[all...] |
| assembler-cond-rd-memop-rs-shift-amount-1to31-a32-ldrb.h | 38 0x86, 0x80, 0xdb, 0x57 // ldrb pl r8 r11 plus r6 LSL 1 Offset
41 0x85, 0x40, 0xd8, 0xd7 // ldrb le r4 r8 plus r5 LSL 1 Offset
44 0x8e, 0x20, 0xd6, 0x67 // ldrb vs r2 r6 plus r14 LSL 1 Offset
47 0x88, 0x10, 0xd7, 0x97 // ldrb ls r1 r7 plus r8 LSL 1 Offset
50 0x8e, 0xe0, 0xd6, 0xa7 // ldrb ge r14 r6 plus r14 LSL 1 Offset
53 0x87, 0x70, 0xd0, 0x27 // ldrb cs r7 r0 plus r7 LSL 1 Offset
56 0x89, 0xb0, 0xd0, 0xa7 // ldrb ge r11 r0 plus r9 LSL 1 Offset
59 0x84, 0x70, 0xda, 0x07 // ldrb eq r7 r10 plus r4 LSL 1 Offset
62 0x83, 0x90, 0xd2, 0xe7 // ldrb al r9 r2 plus r3 LSL 1 Offset
65 0x86, 0xb0, 0xda, 0x37 // ldrb cc r11 r10 plus r6 LSL 1 Offse
[all...] |
| assembler-cond-rd-memop-rs-shift-amount-1to32-a32-ldrb.h | 38 0xa6, 0x80, 0xdb, 0x57 // ldrb pl r8 r11 plus r6 LSR 1 Offset
41 0xa5, 0x40, 0xd8, 0xd7 // ldrb le r4 r8 plus r5 LSR 1 Offset
44 0xae, 0x20, 0xd6, 0x67 // ldrb vs r2 r6 plus r14 LSR 1 Offset
47 0xa8, 0x10, 0xd7, 0x97 // ldrb ls r1 r7 plus r8 LSR 1 Offset
50 0xae, 0xe0, 0xd6, 0xa7 // ldrb ge r14 r6 plus r14 LSR 1 Offset
53 0xa7, 0x70, 0xd0, 0x27 // ldrb cs r7 r0 plus r7 LSR 1 Offset
56 0xa9, 0xb0, 0xd0, 0xa7 // ldrb ge r11 r0 plus r9 LSR 1 Offset
59 0xa4, 0x70, 0xda, 0x07 // ldrb eq r7 r10 plus r4 LSR 1 Offset
62 0xa3, 0x90, 0xd2, 0xe7 // ldrb al r9 r2 plus r3 LSR 1 Offset
65 0xa6, 0xb0, 0xda, 0x37 // ldrb cc r11 r10 plus r6 LSR 1 Offse
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ |
| uread.asm | 28 ldrb r1, [r0]
29 ldrb r2, [r0, #1]
30 ldrb r3, [r0, #2]
31 ldrb r0, [r0, #3]
47 ldrb r1, [r3]
48 ldrb r2, [r3, #1]
50 ldrb r2, [r3, #2]
52 ldrb r0, [r3, #3]
55 ldrb r1, [r3, #4]
56 ldrb r2, [r3, #5]
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| group-reloc-ldr-encoding-bad.s | 24 @ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend.
28 ldrtest ldrb strb f "+ 4096"
30 ldrtest ldrb strb f "- 4096"
33 ldrtest ldrb strb localsym "+ 4096"
35 ldrtest ldrb strb localsym "- 4096"
|
| group-reloc-ldr-parsing-bad.s | 17 ldrb r0, [r0, #:pc_g0_nc:(f)]
18 ldrb r0, [r0, #:pc_g1_nc:(f)]
19 ldrb r0, [r0, #:sb_g0_nc:(f)]
20 ldrb r0, [r0, #:sb_g1_nc:(f)]
31 ldrb r0, [r0, #:foo:(f)]
|
| group-reloc-ldr.s | 23 @ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend.
27 ldrtest ldrb strb f "+ 4095"
29 ldrtest ldrb strb f "- 4095"
35 ldrtest ldrb strb localsym "+ 4095"
37 ldrtest ldrb strb localsym "- 4095"
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| unaligned_load_store.ll | 11 ; GENERIC: ldrb [[R2:r[0-9]+]]
12 ; GENERIC: ldrb [[R3:r[0-9]+]]
13 ; GENERIC: ldrb [[R12:r[0-9]+]]
14 ; GENERIC: ldrb [[R1:r[0-9]+]]
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/epiphany/ |
| badpostmod.s | 13 ldrb r12,[r12],20 ; ERROR
|
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-ldrb.ll | 6 ; CHECK: ldrb r0, [r0]
14 ; CHECK: ldrb r0, [r0, #-1]
24 ; CHECK: ldrb r0, [r0, r1]
34 ; CHECK: ldrb r0, [r0, #-128]
44 ; CHECK: ldrb r0, [r0, r1]
54 ; CHECK: ldrb.w r0, [r0, r1, lsl #2]
66 ; CHECK: ldrb r0, [r0, r1]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
| thumb2-ldrb.ll | 6 ; CHECK: ldrb r0, [r0]
14 ; CHECK: ldrb r0, [r0, #-1]
24 ; CHECK: ldrb r0, [r0, r1]
34 ; CHECK: ldrb r0, [r0, #-128]
44 ; CHECK: ldrb r0, [r0, r1]
54 ; CHECK: ldrb.w r0, [r0, r1, lsl #2]
66 ; CHECK: ldrb r0, [r0, r1]
|
| /external/llvm/test/MC/ARM/ |
| thumb2-ldrb-ldrh.s | 14 ldrb pc, [r0, #10]
15 ldrb.w pc, [r1, #10]
16 ldrb pc, [r2, #-5]
17 ldrb pc, [pc, #7]
18 ldrb.w pc, [pc, #7]
|
| /external/llvm/test/CodeGen/AArch64/ |
| subs-to-sub-opt.ll | 8 ; CHECK: ldrb {{.*}}
9 ; CHECK-NEXT: ldrb {{.*}}
|
| bool-loads.ll | 10 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
22 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
37 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
51 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
|
| /external/llvm/test/CodeGen/ARM/ |
| struct_byval_arm_t1_t2.ll | 54 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
56 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
58 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1
60 ;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}}
63 ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1
140 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
143 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
163 ;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1
165 ;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1
167 ;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #
[all...] |
| /external/llvm/test/CodeGen/Thumb/ |
| ldr_ext.ll | 7 ; V5: ldrb
9 ; V6: ldrb
25 ; V5: ldrb
29 ; V6: ldrb
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb/ |
| ldr_ext.ll | 7 ; V5: ldrb
9 ; V6: ldrb
25 ; V5: ldrb
29 ; V6: ldrb
|
| /external/boringssl/ios-arm/crypto/fipsmodule/ |
| aes-armv4.S | 185 ldrb r0,[r12,#3] @ load input data in endian-neutral
186 ldrb r4,[r12,#2] @ manner...
187 ldrb r5,[r12,#1]
188 ldrb r6,[r12,#0]
190 ldrb r1,[r12,#7]
192 ldrb r4,[r12,#6]
194 ldrb r5,[r12,#5]
195 ldrb r6,[r12,#4]
197 ldrb r2,[r12,#11]
199 ldrb r4,[r12,#10
[all...] |
| /external/boringssl/linux-arm/crypto/fipsmodule/ |
| aes-armv4.S | 184 ldrb r0,[r12,#3] @ load input data in endian-neutral
185 ldrb r4,[r12,#2] @ manner...
186 ldrb r5,[r12,#1]
187 ldrb r6,[r12,#0]
189 ldrb r1,[r12,#7]
191 ldrb r4,[r12,#6]
193 ldrb r5,[r12,#5]
194 ldrb r6,[r12,#4]
196 ldrb r2,[r12,#11]
198 ldrb r4,[r12,#10
[all...] |
| /external/boringssl/src/crypto/fipsmodule/aes/asm/ |
| aes-armv4.pl | 214 ldrb $s0,[$rounds,#3] @ load input data in endian-neutral
215 ldrb $t1,[$rounds,#2] @ manner...
216 ldrb $t2,[$rounds,#1]
217 ldrb $t3,[$rounds,#0]
219 ldrb $s1,[$rounds,#7]
221 ldrb $t1,[$rounds,#6]
223 ldrb $t2,[$rounds,#5]
224 ldrb $t3,[$rounds,#4]
226 ldrb $s2,[$rounds,#11]
228 ldrb $t1,[$rounds,#10
[all...] |
