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  /external/llvm/test/TableGen/
cast.td 63 def VR128 : RegisterClass<[v2i64, v2f64],
73 def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
75 [(set VR128:$dst, (!cast<Intrinsic>(!strconcat(Intr, "_ps")) VR128:$src1, VR128:$src2))]>;
77 def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2)
    [all...]
TargetInstrSpec.td 4 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
5 // CHECK-NOT: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
7 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
8 // CHECK-NOT: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))
    [all...]
usevalname.td 12 def VR128 : Reg;
24 defm ADD : shuffle<VR128>;
MultiPat.td 67 def VR128 : RegisterClass<[v2i64, v2f64],
98 !subst(REGCLASS, VR128,
103 !subst(REGCLASS, VR128,
107 def PS : Base<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
110 def PD : Base<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
120 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))
    [all...]
  /external/swiftshader/third_party/LLVM/test/TableGen/
cast.td 58 def VR128 : RegisterClass<[v2i64, v2f64],
68 def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
70 [(set VR128:$dst, (!cast<Intrinsic>(!strconcat(Intr, "_ps")) VR128:$src1, VR128:$src2))]>;
72 def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2)
    [all...]
TargetInstrSpec.td 1 // RUN: llvm-tblgen %s | grep {\\\[(set VR128:\$dst, (int_x86_sse2_add_pd VR128:\$src1, VR128:\$src2))\\\]} | count 1
2 // RUN: llvm-tblgen %s | grep {\\\[(set VR128:\$dst, (int_x86_sse2_add_ps VR128:\$src1, VR128:\$src2))\\\]} | count 1
59 def VR128 : RegisterClass<[v2i64, v2f64],
81 def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2)
    [all...]
usevalname.td 12 def VR128 : Reg;
24 defm ADD : shuffle<VR128>;
MultiPat.td 67 def VR128 : RegisterClass<[v2i64, v2f64],
98 !subst(REGCLASS, VR128,
103 !subst(REGCLASS, VR128,
107 def PS : Base<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
110 def PD : Base<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
120 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))
    [all...]
  /external/llvm/lib/Target/X86/
X86InstrXOP.td 15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
17 [(set VR128:$dst, (Int VR128:$src))]>, XOP;
18 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
20 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
44 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
46 [(set VR128:$dst, (Int VR128:$src))]>, XOP
    [all...]
X86InstrSSE.td 333 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
335 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
358 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
359 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>
    [all...]
X86InstrFMA.td 43 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
44 (ins VR128:$src1, VR128:$src2, VR128:$src3),
47 [(set VR128:$dst, (OpVT128 (Op VR128:$src2,
48 VR128:$src1, VR128:$src3)))]>;
51 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
52 (ins VR128:$src1, VR128:$src2, f128mem:$src3)
    [all...]
X86InstrMMX.td 304 (ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}",
307 (i64 (extractelt (v2i64 VR128:$src),
311 def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst),
313 [(set VR128:$dst,
582 defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
585 defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
588 defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
591 defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
594 defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
598 defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
    [all...]
X86RegisterInfo.td 466 // Generic vector registers: VR64 and VR128.
469 def VR128 : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64],
504 // Extended VR128 and VR256 for AVX-512 instructions
  /external/swiftshader/third_party/LLVM/lib/Target/X86/
X86InstrSSE.td 123 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
124 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
125 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
126 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
147 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
148 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
149 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
150 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
151 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
152 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
    [all...]
X86InstrFMA.td 19 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
20 (ins VR128:$src1, VR128:$src2),
23 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
24 (ins VR128:$src1, f128mem:$src2),
X86InstrMMX.td 191 def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
195 (i64 (vector_extract (v2i64 VR128:$src),
198 def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
200 [(set VR128:$dst,
371 defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
374 defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
377 defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
380 defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
383 defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
387 defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
    [all...]
X86GenDAGISel.inc 34 // Src: (st VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity = 422
35 // Dst: (VMOVNTPSmr addr:iPTR:$dst, VR128:v4f32:$src)
39 // Src: (st VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity = 422
40 // Dst: (VMOVNTDQmr addr:iPTR:$dst, VR128:v4f32:$src)
48 // Src: (st VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity = 422
49 // Dst: (MOVNTPSmr addr:iPTR:$dst, VR128:v4f32:$src)
56 // Src: (st VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity = 422
57 // Dst: (MOVNTDQmr addr:iPTR:$dst, VR128:v4f32:$src)
70 // Src: (st VR128:v2f64:$src, addr:iPTR:$dst)<<P:Predicate_alignednontemporalstore>> - Complexity = 422
71 // Dst: (VMOVNTPDmr addr:iPTR:$dst, VR128:v2f64:$src)
    [all...]
X86InstrCompiler.td     [all...]
X86RegisterInfo.td 458 // Generic vector registers: VR64 and VR128.
460 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
467 let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)];
  /external/llvm/lib/Target/SystemZ/
SystemZInstrVector.td 45 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)),
46 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>;
153 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index),
154 (VLEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>;
155 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index),
156 (VLEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>;
201 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr,
203 (VSTEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>;
204 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr,
206 (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>
    [all...]
SystemZRegisterInfo.td 219 class VR128<bits<16> num, string n, FPR64 high>
227 def V#I : VR128<I, "v"#I, !cast<FPR64>("F"#I#"D")>,
253 defm VR128 : SystemZRegClass<"VR128",
269 def v128b : TypedReg<v16i8, VR128>;
270 def v128h : TypedReg<v8i16, VR128>;
271 def v128f : TypedReg<v4i32, VR128>;
272 def v128g : TypedReg<v2i64, VR128>;
273 def v128q : TypedReg<v16i8, VR128>;
274 def v128eb : TypedReg<v4f32, VR128>;
    [all...]
SystemZInstrFormats.td 1049 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
1088 : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
1154 : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
1156 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
    [all...]
  /external/llvm/lib/Target/SystemZ/MCTargetDesc/
SystemZMCTargetDesc.h 76 // Return the given register as a VR128.
  /external/llvm/utils/TableGen/
X86RecognizableInstr.cpp 948 TYPE("VR128", TYPE_XMM128)
    [all...]
  /external/swiftshader/third_party/LLVM/utils/TableGen/
X86RecognizableInstr.cpp     [all...]

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