| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| half-prec-psyntax.s | 4 vcvtt s2.f32, s5.f16
6 vcvtt s2.f16, s5.f32
|
| half-prec-psyntax.d | 10 0+08 <[^>]*> eeb21ae2 vcvtt\.f32\.f16 s2, s5
12 0+10 <[^>]*> eeb31ae2 vcvtt\.f16\.f32 s2, s5
|
| armv8-a+fp.s | 53 vcvtt.f16.f64 s0, d0
55 vcvtt.f16.f64 s30, d15
57 vcvtt.f64.f16 d0, s0
59 vcvtt.f64.f16 d15, s30
109 vcvtt.f16.f64 s0, d0
111 vcvtt.f16.f64 s30, d15
113 vcvtt.f64.f16 d0, s0
115 vcvtt.f64.f16 d15, s30
|
| half-prec-vfpv3.s | 2 vcvtt.f32.f16 s0, s1
19 vcvtt.f16.f32 s0, s1
|
| half-prec-vfpv3.d | 8 0+000 <[^>]*> eeb20ae0 vcvtt.f32.f16 s0, s1
23 0+03c <[^>]*> eeb21ae1 vcvtt.f32.f16 s2, s3
24 0+040 <[^>]*> eeb30ae0 vcvtt.f16.f32 s0, s1
39 0+07c <[^>]*> eeb31ae1 vcvtt.f16.f32 s2, s3
|
| armv8-a+fp.d | 54 0[0-9a-f]+ <[^>]+> eeb30bc0 vcvtt.f16.f64 s0, d0
56 0[0-9a-f]+ <[^>]+> eeb3fbcf vcvtt.f16.f64 s30, d15
58 0[0-9a-f]+ <[^>]+> eeb20bc0 vcvtt.f64.f16 d0, s0
60 0[0-9a-f]+ <[^>]+> eeb2fbcf vcvtt.f64.f16 d15, s30
108 0[0-9a-f]+ <[^>]+> eeb3 0bc0 vcvtt.f16.f64 s0, d0
110 0[0-9a-f]+ <[^>]+> eeb3 fbcf vcvtt.f16.f64 s30, d15
112 0[0-9a-f]+ <[^>]+> eeb2 0bc0 vcvtt.f64.f16 d0, s0
114 0[0-9a-f]+ <[^>]+> eeb2 fbcf vcvtt.f64.f16 d15, s30
|
| /external/llvm/test/tools/llvm-objdump/ARM/ |
| macho-mattr-arm.test | 3 vcvtt.f64.f16 d3, s1
5 @ CHECK: e0 3b b2 ee vcvtt.f64.f16 d3, s1
|
| /external/llvm/test/MC/ARM/ |
| neon-vcvt-fp16.s | 6 @ CHECK-FP16: vcvtt.f32.f16 s7, s1 @ encoding: [0xe0,0x3a,0xf2,0xee]
8 vcvtt.f32.f16 s7, s1
9 @ CHECK-FP16: vcvtt.f16.f32 s1, s7 @ encoding: [0xe3,0x0a,0xf3,0xee]
11 vcvtt.f16.f32 s1, s7
|
| invalid-fp-armv8.s | 5 vcvtt.f64.f16 d3, s1
6 @ V7-NOT: vcvtt.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xee]
7 vcvtt.f16.f64 s5, d12
8 @ V7-NOT: vcvtt.f16.f64 s5, d12 @ encoding: [0xcc,0x2b,0xf3,0xee]
|
| fp-armv8.s | 5 vcvtt.f64.f16 d3, s1
6 @ CHECK: vcvtt.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xee]
7 vcvtt.f16.f64 s5, d12
8 @ CHECK: vcvtt.f16.f64 s5, d12 @ encoding: [0xcc,0x2b,0xf3,0xee]
|
| thumb-fp-armv8.s | 5 vcvtt.f64.f16 d3, s1
6 @ CHECK: vcvtt.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0xe0,0x3b]
7 vcvtt.f16.f64 s5, d12
8 @ CHECK: vcvtt.f16.f64 s5, d12 @ encoding: [0xf3,0xee,0xcc,0x2b]
|
| directive-arch_extension-fp.s | 52 vcvtt.f64.f16 d0, s0
54 vcvtt.f16.f64 s0, d0
188 vcvtt.f64.f16 d0, s0
190 vcvtt.f16.f64 s0, d0
|
| single-precision-fp.s | 141 vcvtt.f64.f16 d11, s12
142 vcvtt.f16.f64 s13, d14
148 @ CHECK-ERRORS-NEXT: vcvtt.f64.f16 d11, s12
150 @ CHECK-ERRORS-NEXT: vcvtt.f16.f64 s13, d14
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| invalid-because-armv7.txt | 7 # Would be vcvtt.f64.f16 d3, s1
|
| fp-armv8.txt | 4 # CHECK: vcvtt.f64.f16 d3, s1
7 # CHECK: vcvtt.f16.f64 s5, d12
|
| thumb-fp-armv8.txt | 4 # CHECK: vcvtt.f64.f16 d3, s1
7 # CHECK: vcvtt.f16.f64 s5, d12
|
| /external/valgrind/none/tests/arm/ |
| v8fpsimd_a.c | 321 GEN_TWOVEC_QDS_TEST(vcvtt_f64_f16, IT_AL, "vcvtt.f64.f16 d28, s17", 14, 4)
324 GEN_TWOVEC_QDS_TEST(vcvtt_f16_f64, IT_AL, "vcvtt.f16.f64 s8, d27", 2, 13)
|
| v8fpsimd_t.c | 321 GEN_TWOVEC_QDS_TEST(vcvtt_f64_f16, IT_AL, "vcvtt.f64.f16 d28, s17", 14, 4)
324 GEN_TWOVEC_QDS_TEST(vcvtt_f16_f64, IT_AL, "vcvtt.f16.f64 s8, d27", 2, 13)
|
| /prebuilts/go/darwin-x86/pkg/darwin_amd64/cmd/vendor/golang.org/x/arch/arm/ |
| armasm.a | [all...] |
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| tables.go | [all...] |
| /prebuilts/go/linux-x86/pkg/linux_amd64/cmd/vendor/golang.org/x/arch/arm/ |
| armasm.a | [all...] |
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| tables.go | [all...] |
| /external/vixl/src/aarch32/ |
| constants-aarch32.cc | 608 return "vcvtt";
|
| assembler-aarch32.h | 4281 void vcvtt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { function in class:vixl::aarch32::Assembler
4287 void vcvtt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { function in class:vixl::aarch32::Assembler
4293 void vcvtt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { function in class:vixl::aarch32::Assembler
[all...] |
| disasm-aarch32.h | [all...] |
