| /external/llvm/test/CodeGen/XCore/ |
| unaligned_store.ll | 4 ; CHECK-LABEL: align1:
6 define void @align1(i32* %p, i32 %val) nounwind {
|
| unaligned_load.ll | 4 ; CHECK: align1
6 define i32 @align1(i32* %p) nounwind {
|
| /external/llvm/test/Analysis/ValueTracking/ |
| memory-dereferenceable.ll | 19 @globalptr.align1 = external global i8, align 1
24 i8 addrspace(1)* dereferenceable(32) align 1 %dparam.align1,
86 ; CHECK: @globalptr.align1{{.*}}(unaligned)
88 %load13 = load i8, i8* @globalptr.align1, align 16
92 ; CHECK: %dparam.align1{{.*}}(unaligned)
94 %load15 = load i8, i8 addrspace(1)* %dparam.align1, align 16
98 ; CHECK: %alloca.align1{{.*}}(unaligned)
100 %alloca.align1 = alloca i1, align 1
102 %load17 = load i1, i1* %alloca.align1, align 16
106 ; CHECK: %gep.align1.offset1{{.*}}(unaligned
[all...] |
| /external/swiftshader/third_party/LLVM/test/CodeGen/XCore/ |
| unaligned_store.ll | 7 define void @align1(i32* %p, i32 %val) nounwind {
|
| unaligned_load.ll | 11 define i32 @align1(i32* %p) nounwind {
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_schedule_instructions.cpp | 221 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
224 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
225 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
234 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
237 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
238 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
250 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
251 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
253 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
256 * mov(8) g115<1>F 0F { align1 WE_normal 1Q }
[all...] |
| brw_eu_emit.c | 186 /* These are different sizes in align1 vs align16:
2954 const bool align1 = brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_1; local
3055 const bool align1 = brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_1; local
3113 const bool align1 = (brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_1); local
3224 const bool align1 = (brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_1); local
3458 const bool align1 = brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_1; local
[all...] |
| brw_vec4_generator.cpp | 436 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
479 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
566 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
622 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
647 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
[all...] |
| brw_reg.h | 240 * Align1 operation has a lot of control over input ranges. Used in
265 unsigned width:3; /* src only, align1 only */
266 unsigned hstride:2; /* align1 only */
|
| brw_vec4_visitor.cpp | 355 /* MATH on Gen6 must be align1, so we can't do writemasks. */
387 * align1 mode, because only in align1 mode is it possible to specify
391 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
461 * which is only possible in align1 mode. All my [chadv] attempts at
462 * emitting align1 instructions for unpackHalf2x16 failed to pass the
[all...] |
| brw_inst.h | 659 /* AddrImm[9:0] for Align1 Indirect Addressing */
691 * Compared to Align1, these are missing the low 4 bits.
|
| brw_vec4_copy_propagation.cpp | 381 /* Instructions that operate on vectors in ALIGN1 mode will ignore swizzles
|
| /external/llvm/test/Transforms/MergeFunc/ |
| alloca.ll | 39 ; CHECK-LABEL: define void @align1
41 define void @align1(i8 *%f) {
|
| /external/clang/test/CodeGen/ |
| palignr.c | 8 int4 align1(int4 a, int4 b) { return _mm_alignr_epi8(a, b, 15); } function
|
| packed-arrays.c | 28 // CHECK: @align1 = local_unnamed_addr global i32 4
29 int align1 = __alignof(struct s1); variable
|
| arm64-arguments.c | 682 // CHECK: [[ALIGN1:%.*]] = add i64 [[ALIGN0]], 15
683 // CHECK: [[ALIGN2:%.*]] = and i64 [[ALIGN1]], -16
729 // CHECK: [[ALIGN1:%.*]] = add i64 [[ALIGN0]], 15
730 // CHECK: [[ALIGN2:%.*]] = and i64 [[ALIGN1]], -16
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-scripts/ |
| align.exp | 27 set testname "align1"
|
| /external/llvm/lib/Transforms/IPO/ |
| Inliner.cpp | 161 unsigned Align1 = AI->getAlignment(),
189 if (Align1 != Align2) {
190 if (!Align1 || !Align2) {
194 Align1 = Align1 ? Align1 : TypeAlign;
198 if (Align1 > Align2)
|
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.cpp | 64 ALIGN1 = 0,
73 AlignVariant = ALIGN1;
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/hppa/parse/ |
| parse.exp | 82 set testname "align1.s: valid alignment tests"
85 gas_start "align1.s" "-al"
|
| /external/syslinux/core/lzo/ |
| lzo_asm.h | 125 #define ALIGN1 LZO_ASM_ALIGN(1)
|
| lzo1x_d.ash | 250 ALIGN1
|
| /external/mesa3d/src/gallium/drivers/ilo/shader/ |
| toy_legalize.c | 87 /* no swizzling in align1 */
110 /* no writemask in align1 */
|
| /external/llvm/test/Bitcode/ |
| ssse3_palignr.ll | 5 define <4 x i32> @align1(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
|
| /external/swiftshader/third_party/subzero/src/ |
| IceCfg.cpp | 917 uint32_t Align1 = A1->getAlignInBytes();
919 if (Align1 == Align2)
922 return Align1 > Align2;
[all...] |
