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  /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
64bit.pnacl.ll 567 ; MIPS32: sllv [[T1:.*]],[[A_HI:.*]],[[B_LO:.*]]
568 ; MIPS32: nor [[T2:.*]],[[B_LO]],zero
572 ; MIPS32: sllv [[T_LO:.*]],[[A_LO]],[[B_LO]]
574 ; MIPS32: andi [[T5:.*]],[[B_LO]],0x20
634 ; MIPS32: sllv [[T1:.*]],[[A_HI:.*]],[[B_LO:.*]]
635 ; MIPS32: nor [[T2:.*]],[[B_LO]],zero
639 ; MIPS32: sllv [[T_LO:.*]],[[A_LO]],[[B_LO]]
641 ; MIPS32: andi [[T5:.*]],[[B_LO]],0x20
677 ; MIPS32: srlv [[T1:.*]],[[A_LO:.*]],[[B_LO:.*]]
678 ; MIPS32: nor [[T2:.*]],[[B_LO]],zer
    [all...]
  /frameworks/rs/cpu_ref/
rsCpuIntrinsics_advsimd_YuvToRGB.S 33 * v2 out B_lo / even B_lo accumulator
44 * v13 B_lo luma tmp
49 * v18 odd B_lo accumulator
  /art/compiler/optimizing/
intrinsics_mips.cc 1129 Register b_lo = locations->InAt(1).AsRegisterPairLow<Register>(); local
1194 Register b_lo = locations->InAt(1).AsRegisterPairLow<Register>(); local
    [all...]
  /external/llvm/test/CodeGen/AMDGPU/
llvm.amdgcn.div.scale.ll 277 ; SI-DAG: s_load_dwordx2 s{{\[}}[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xd
278 ; SI-DAG: v_mov_b32_e32 v[[VB_LO:[0-9]+]], s[[B_LO]]
  /external/webp/src/dsp/
lossless_enc_sse2.c 582 const __m128i B_lo = _mm_unpacklo_epi32(*B, *A);
585 const __m128i s_lo = _mm_sad_epu8(A_lo, B_lo);
lossless_sse2.c 309 const __m128i B_lo = _mm_unpacklo_epi32(*B, *A);
312 const __m128i s_lo = _mm_sad_epu8(A_lo, B_lo);
  /external/swiftshader/third_party/subzero/src/
IceTargetLoweringX86BaseImpl.h     [all...]

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