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  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/m68k/
p3041pcrel.d 16 2: DISP16 mytext
18 6: DISP16 mytext
20 a: DISP16 mytext
22 e: DISP16 mydata
24 12: DISP16 mydata
26 16: DISP16 mydata
28 1a: DISP16 mybss
30 1e: DISP16 mybss
32 22: DISP16 mybss
  /toolchain/binutils/binutils-2.25/opcodes/
i386-opc.tbl 25 mov, 2, 0xa0, None, 1, CpuNo64, D|W|CheckRegSize|No_sSuf|No_qSuf|No_ldSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword }
26 mov, 2, 0x88, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixOk=3, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
30 mov, 2, 0xc6, 0x0, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixOk=3, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
38 mov, 2, 0x8c, None, 1, 0, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg2, Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
40 mov, 2, 0x8c, None, 1, Cpu386, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg3, Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
42 mov, 2, 0x8e, None, 1, 0, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, SReg2 }
44 mov, 2, 0x8e, None, 1, Cpu386, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, SReg3 }
56 movbe, 2, 0x0f38f0, None, 3, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
57 movbe, 2, 0x0f38f1, None, 3, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
62 movsbl, 2, 0xfbe, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32
    [all...]
h8500-opc.h 136 #define DISP16 30
180 {3,'m','E','D','D',O_XOR|O_WORD,"xor.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x60,0xf8,RD }}},
189 {4,'m','E','D','D',O_XOR|O_BYTE,"xor.b",2,{RNIND_D16,RD},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x60,0xf8,RD }}},
198 {5,'m','E','D','D',O_XOR|O_UNSZ,"xor",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x60,0xf8,RD }}},
210 {9,'a','E','!','!',O_TST|O_WORD,"tst.w",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x16,0xff,0 }}},
219 {10,'a','E','!','!',O_TST|O_BYTE,"tst.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x16,0xff,0 }}},
228 {11,'a','E','!','!',O_TST|O_UNSZ,"tst",1,{RNIND_D16,0},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x16,0xff,0 }}},
239 {14,'s','E','!','E',O_TAS|O_BYTE,"tas.b",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x17,0xff,0 }}},
248 {15,'s','E','!','E',O_TAS|O_UNSZ,"tas",1,{RNIND_D16,0},4, {{0xf0,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0x17,0xff,0 }}},
259 {18,'a','E','D','D',O_SUBX|O_WORD,"subx.w",2,{RNIND_D16,RD},4, {{0xf8,0xf8,RN },{0x00,0x00,DISP16 },{0x00,0x00,0 },{0xb0,0xf8,RD }}}
    [all...]
m32r-opc.c 306 /* beq $src1,$src2,$disp16 */
309 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
312 /* beqz $src2,$disp16 */
315 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
318 /* bgez $src2,$disp16 */
321 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
324 /* bgtz $src2,$disp16 */
327 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
330 /* blez $src2,$disp16 */
333 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }
    [all...]
m32r-desc.c 281 { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
409 /* disp16: 16 bit displacement */
410 { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
515 /* beq $src1,$src2,$disp16 */
520 /* beqz $src2,$disp16 */
525 /* bgez $src2,$disp16 */
530 /* bgtz $src2,$disp16 */
535 /* blez $src2,$disp16 */
540 /* bltz $src2,$disp16 */
545 /* bnez $src2,$disp16 */
    [all...]
z8kgen.c 292 {"------", 15, 16, "0011 0100 0000 dddd disp16", "ldar prd,disp16", 0},
309 {"------", 14, 16, "0011 0011 0000 ssss disp16", "ldr disp16,rs", 0},
310 {"------", 14, 16, "0011 0001 0000 dddd disp16", "ldr rd,disp16", 0},
311 {"------", 14, 8, "0011 0010 0000 ssss disp16", "ldrb disp16,rbs", 0},
312 {"------", 14, 8, "0011 0000 0000 dddd disp16", "ldrb rbd,disp16", 0}
    [all...]
h8500-dis.c 142 case DISP16:
i386-gen.c 281 "Disp16" },
331 "Disp16|Disp32" },
333 "Disp8|Disp16|Disp32|Disp32S|Disp64" },
543 BITFIELD (Disp16),
    [all...]
m32r-opinst.c 119 { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
127 { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
    [all...]
z8k-opc.h     [all...]
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/pdp11/
absreloc.d 12 8: 0bf7 0008 tst \$14 <start\+0x14> a: DISP16 \*ABS\*
14 10: 0bf7 0000 tst \$14 <start\+0x14> 12: DISP16 \*ABS\*
  /toolchain/binutils/binutils-2.25/include/aout/
reloc.h 54 "DISP16", "DISP32", "WDISP30", "WDISP22", \
  /toolchain/binutils/binutils-2.25/bfd/
coff-we32k.c 52 HOWTO(R_PCRWORD, 0, 1, 16, TRUE, 0, complain_overflow_signed, 0, "DISP16", TRUE, 0x0000ffff,0x0000ffff, FALSE),
coff-apollo.c 41 HOWTO (R_PCRWORD, 0, 1, 16, TRUE, 0, complain_overflow_signed, 0, "DISP16", TRUE, 0x0000ffff,0x0000ffff, FALSE),
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cr16/
loadb_test.s 44 # loadb rpbase(disp4/disp16/disp20/-disp20) reg
loadd_test.s 44 # loadd rpbase(disp4/disp16/disp20/-disp20) reg
loadw_test.s 44 # loadw rpbase(disp4/disp16/disp20/-disp20) reg
stord_test.s 44 # stord regp rpbase(disp4/disp16/disp20/-disp20)
storb_test.s 44 # storb reg rpbase(disp4/disp16/disp20/-disp20)
storw_test.s 44 # storw reg rpbase(disp4/disp16/disp20/-disp20)
  /toolchain/binutils/binutils-2.25/gas/doc/
c-z8k.texi 340 ldar rd,disp16 ldps addr(rs) outibr @@rd,@@rs,ra
341 ldb @@rd,imm8 ldr disp16,rs pop @@rd,@@rs
342 ldb @@rd,rbs ldr rd,disp16 pop addr(rd),@@rs
343 ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@@rs
344 ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@@rs
345 ldb addr,imm8 ldrl disp16,rrs popl @@rd,@@rs
346 ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@@rs
  /external/elfutils/backends/
sparc_reloc.def 36 RELOC_TYPE (DISP16, REL)
  /toolchain/binutils/binutils-2.25/cpu/
m32r.cpu 486 (df f-disp16 "disp16" (PCREL-ADDR RELOC) 16 16 INT
749 (dnop disp16 "16 bit displacement" () h-iaddr f-disp16)
925 "beq $src1,$src2,$disp16"
926 (+ OP1_11 OP2_0 src1 src2 disp16)
927 (if (eq src1 src2) (set pc disp16))
935 (.str sym " $src2,$disp16")
936 (+ OP1_11 op2-op (f-r1 0) src2 disp16)
937 (if (comp-op src2 (const WI 0)) (set pc disp16))
    [all...]
  /prebuilts/go/darwin-x86/src/cmd/internal/obj/s390x/
a.out.go 156 DISP16 = 65536
  /prebuilts/go/linux-x86/src/cmd/internal/obj/s390x/
a.out.go 156 DISP16 = 65536

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