| /prebuilts/go/darwin-x86/src/math/ |
| sqrt_arm64.s | 10 FSQRTD F0, F0
|
| /prebuilts/go/linux-x86/src/math/ |
| sqrt_arm64.s | 10 FSQRTD F0, F0
|
| /external/llvm/test/CodeGen/ARM/ |
| inlineasm2.ll | 4 %tmp2 = tail call double asm "fsqrtd ${0:P}, ${1:P}", "=w,w"( double %x )
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| inlineasm2.ll | 4 %tmp2 = tail call double asm "fsqrtd ${0:P}, ${1:P}", "=w,w"( double %x )
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| vfpv3-32drs.s | 31 fsqrtd d3,d5
32 fsqrtd d12,d18
33 fsqrtd d18,d19
|
| vfpv3-32drs.d | 36 0[0-9a-f]+ <[^>]+> eeb13bc5 (vsqrt\.f64|fsqrtd) d3, d5
37 0[0-9a-f]+ <[^>]+> eeb1cbe2 (vsqrt\.f64|fsqrtd) d12, d18
38 0[0-9a-f]+ <[^>]+> eef12be3 (vsqrt\.f64|fsqrtd) d18, d19
|
| vfpv3-d16-bad.l | 26 [^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fsqrtd d12,d18'
27 [^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fsqrtd d18,d19'
|
| vfp1.s | 21 fsqrtd d0, d0
|
| vfp1_t2.s | 24 fsqrtd d0, d0
|
| vfp1.d | 17 0+01c <[^>]*> eeb10bc0 (vsqrt\.f64|fsqrtd) d0, d0
|
| vfp1_t2.d | 17 0+01c <[^>]*> eeb1 0bc0 (vsqrt\.f64|fsqrtd) d0, d0
|
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/arm64/ |
| anames.go | 303 "FSQRTD",
|
| /prebuilts/go/linux-x86/src/cmd/internal/obj/arm64/ |
| anames.go | 303 "FSQRTD",
|
| /external/llvm/lib/Target/Sparc/ |
| LeonPasses.cpp | 341 // 1) fixing the FSQRTS and FSQRTD instructions.
344 // FSQRTS and FDIVS are converted to FDIVD and FSQRTD respectively earlier in
369 if (AsmString.startswith_lower("fsqrtd")) {
371 Opcode = SP::FSQRTD;
380 // already have been converted to FSQRTD or FDIVD earlier in the
382 if (Opcode == SP::FSQRTD || Opcode == SP::FDIVD) {
383 // Insert 5 NOPs before FSQRTD,FDIVD.
388 // ... and inserting 28 NOPs after FSQRTD,FDIVD.
686 } else if (NextOpcode == SP::FSQRTD) {
[all...] |
| LeonFeatures.td | 72 "LEON3 erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD "
|
| LeonPasses.h | 149 return "FixAllFDIVSQRT: Erratum Fix LBR34: fix FDIVS/FDIVD/FSQRTS/FSQRTD "
|
| DelaySlotFiller.cpp | 284 Opcode >= SP::FDIVD && Opcode <= SP::FSQRTD)
|
| /external/llvm/test/MC/Sparc/ |
| sparc-fp-instructions.s | 54 ! CHECK: fsqrtd %f0, %f4 ! encoding: [0x89,0xa0,0x05,0x40]
57 fsqrtd %f0, %f4
|
| /external/llvm/test/MC/Disassembler/Sparc/ |
| sparc-fp.txt | 69 # CHECK: fsqrtd %f0, %f4
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/m68k/ |
| mcf-fpu.s | 4 fsqrtd %fp0,%fp0
23 fsqrtd %a4@,%fp0
24 fsqrtd %a3@+,%fp0
25 fsqrtd %a2@-,%fp0
26 fsqrtd %fp@(8),%fp0
27 fsqrtd %pc@(.+0x1238),%fp0
|
| mcf-fpu.d | 9 [ 0-9a-f]+: f200 0004 fsqrtd %fp0,%fp0
28 [ 0-9a-f]+: f214 5404 fsqrtd %a4@,%fp0
29 [ 0-9a-f]+: f21b 5404 fsqrtd %a3@\+,%fp0
30 [ 0-9a-f]+: f222 5404 fsqrtd %a2@-,%fp0
31 [ 0-9a-f]+: f22e 5404 0008 fsqrtd %fp@\(8\),%fp0
32 [ 0-9a-f]+: f23a 5404 1234 fsqrtd %pc@\(.*\),%fp0
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/frv/ |
| allinsn.s | 2145 .global fsqrtd
2146 fsqrtd: label
2147 fsqrtd fr0,fr0
|
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/ssa/gen/ |
| ARM64Ops.go | 203 {name: "FSQRTD", argLength: 1, reg: fp11, asm: "FSQRTD"}, // sqrt(arg0), float64
|
| /prebuilts/go/linux-x86/src/cmd/compile/internal/ssa/gen/ |
| ARM64Ops.go | 203 {name: "FSQRTD", argLength: 1, reg: fp11, asm: "FSQRTD"}, // sqrt(arg0), float64
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcInstrInfo.td | 631 def FSQRTD : F3_3<2, 0b110100, 0b000101010,
633 "fsqrtd $src, $dst",
[all...] |
