| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUOperands.td | 143 def imm18 : PatLeaf<(imm), [{
144 // imm18 predicate: True if the immediate fits into an 18-bit unsigned field.
|
| SPUInstrInfo.td | 412 def r64: ILARegInst<R64C, u18imm_i64, imm18>;
413 def r32: ILARegInst<R32C, u18imm, imm18>;
417 def hi: ILARegInst<R32C, symbolHi, imm18>;
418 def lo: ILARegInst<R32C, symbolLo, imm18>;
421 [(set R32C:$rT, imm18:$val)]>;
[all...] |
| /external/v8/src/mips/ |
| assembler-mips.cc | 792 int32_t imm18 =((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14;
793 return (imm18 + pos);
1246 int32_t imm18 = target_pos - at_offset; local
[all...] |
| disasm-mips.cc | 591 DCHECK(STRING_STARTS_WITH(format, "imm18"));
[all...] |
| /external/v8/src/mips64/ |
| assembler-mips64.cc | 726 int32_t imm18 =((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14;
727 return (imm18 + pos);
1233 int32_t imm18 = target_pos - at_offset; local
[all...] |
| simulator-mips64.cc | [all...] |
| disasm-mips64.cc | 607 DCHECK(STRING_STARTS_WITH(format, "imm18"));
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64.cc | 594 void Mips64Assembler::Ldpc(GpuRegister rs, uint32_t imm18) {
595 CHECK(IsUint<18>(imm18)) << imm18;
596 EmitI21(0x3B, rs, (0x06 << 18) | imm18);
[all...] |
| assembler_mips64.h | 519 void Ldpc(GpuRegister rs, uint32_t imm18); // MIPS64
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| d30v-opc.c | 434 { SHORT_B2, 2, { IMM18S3 } }, /* imm18 */
|
