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  /external/vixl/src/aarch64/
operands-aarch64.cc 308 VIXL_ASSERT(!reg.IsSP());
319 VIXL_ASSERT(!reg.IsSP());
400 VIXL_ASSERT(!regoffset.IsSP());
420 VIXL_ASSERT(regoffset.Is64Bits() && !regoffset.IsSP());
447 VIXL_ASSERT(regoffset_.Is64Bits() && !regoffset_.IsSP());
461 VIXL_ASSERT(!regoffset_.IsSP());
macro-assembler-aarch64.cc 455 temp = rd.IsSP() ? temps.AcquireSameSizeAs(rd) : rd;
486 if (rd.IsSP()) {
502 if (IsImmMovz(imm, reg_size) && !dst.IsSP()) {
509 } else if (IsImmMovn(imm, reg_size) && !dst.IsSP()) {
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operands-aarch64.h 183 bool IsSP() const {
assembler-aarch64.cc     [all...]
  /external/v8/src/arm64/
assembler-arm64-inl.h 145 inline bool CPURegister::IsSP() const {
337 DCHECK(!reg.IsSP());
349 DCHECK(!reg.IsSP());
465 DCHECK(!regoffset.IsSP());
480 DCHECK(regoffset.Is64Bits() && !regoffset.IsSP());
504 DCHECK(regoffset_.Is64Bits() && !regoffset_.IsSP());
518 DCHECK(!regoffset_.IsSP());
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assembler-arm64.cc     [all...]
macro-assembler-arm64.cc 206 Register temp = rd.IsSP() ? temps.AcquireSameSizeAs(rd) : rd;
232 if (rd.IsSP()) {
249 Register dst = (rd.IsSP()) ? temps.AcquireSameSizeAs(rd) : rd;
290 DCHECK(rd.IsSP());
419 if (IsImmMovz(imm, reg_size) && !dst.IsSP()) {
424 } else if (IsImmMovn(imm, reg_size) && !dst.IsSP()) {
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macro-assembler-arm64-inl.h 460 DCHECK(!rd.IsSP() && rd.Is64Bits());
472 DCHECK(!rd.IsSP());
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assembler-arm64.h 114 bool IsSP() const;
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  /external/icu/icu4c/source/test/cintltst/
cucdtst.c 755 #define ISSP 0x200
785 { 0x0009, ISSP|ISBL|ISCN }, /* TAB */
786 { 0x000a, ISSP| ISCN }, /* LF */
787 { 0x000c, ISSP| ISCN }, /* FF */
788 { 0x000d, ISSP| ISCN }, /* CR */
789 { 0x0020, ISPR|ISSP|ISBL }, /* space */
796 { 0x0085, ISSP| ISCN }, /* NEL */
797 { 0x00a0, ISPR|ISSP|ISBL }, /* NBSP */
804 { 0x2002, ISPR|ISSP|ISBL }, /* en space */
805 { 0x2007, ISPR|ISSP|ISBL }, /* figure space *
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  /art/compiler/utils/arm/
assembler_arm_vixl.cc 328 CHECK(!dest.IsSP());
  /external/mksh/src/
edit.c 4464 #define issp macro
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  /external/vixl/src/aarch32/
instructions-aarch32.h 147 bool IsSP() const { return GetCode() == kSpCode; }
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macro-assembler-aarch32.h     [all...]
  /frameworks/base/services/core/java/com/android/server/pm/
Settings.java     [all...]
  /art/compiler/optimizing/
intrinsics_arm_vixl.cc 215 DCHECK(!tmp.IsSP());
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