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  /external/llvm/test/MC/AMDGPU/
ds-err.s 8 // offset0 twice
10 ds_write2_b32 v2, v4, v6 offset0:4 offset0:8
16 // offset0 too big
18 ds_write2_b32 v2, v4, v6 offset0:1000000000
ds.s 17 ds_write_src2_b32 v2 offset0:4 offset1:8
18 // SICI: ds_write_src2_b32 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x34,0xda,0x02,0x00,0x00,0x00]
19 // VI: ds_write_src2_b32 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x1a,0xd9,0x02,0x00,0x00,0x00]
21 ds_write_src2_b64 v2 offset0:4 offset1:8
22 // SICI: ds_write_src2_b64 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x34,0xdb,0x02,0x00,0x00,0x00]
23 // VI: ds_write_src2_b64 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x9a,0xd9,0x02,0x00,0x00,0x00]
25 ds_write2_b32 v2, v4, v6 offset0:4
26 // SICI: ds_write2_b32 v2, v4, v6 offset0:4 ; encoding: [0x04,0x00,0x38,0xd8,0x02,0x04,0x06,0x00]
27 // VI: ds_write2_b32 v2, v4, v6 offset0:4 ; encoding: [0x04,0x00,0x1c,0xd8,0x02,0x04,0x06,0x00]
29 ds_write2_b32 v2, v4, v6 offset0:4 offset1:
    [all...]
  /development/tools/bugreport/src/com/android/bugreport/stacks/
KernelStackFrameSnapshot.java 24 public int offset0; field in class:KernelStackFrameSnapshot
34 this.offset0 = that.offset0;
  /external/clang/test/CodeGen/
arm64-be-hfa-vararg.c 9 // CHECK: [[OFFSET0:%.*]] = getelementptr inbounds i8, i8* [[REGP]], i32 {{.*}}
10 // CHECK: [[OFFSET1:%.*]] = getelementptr inbounds i8, i8* [[OFFSET0]], i64 8
  /external/skia/tests/
PipeTest.cpp 59 size_t offset0 = stream.bytesWritten(); local
60 REPORTER_ASSERT(reporter, offset0 > 100); // the raw image must be sorta big
95 size_t offset0 = data->size(); local
96 REPORTER_ASSERT(reporter, offset0 > 100); // the raw image must be sorta big
130 size_t offset0 = stream.bytesWritten(); local
131 REPORTER_ASSERT(reporter, offset0 > 100); // the raw picture must be sorta big
170 size_t offset0 = data->size(); local
171 REPORTER_ASSERT(reporter, offset0 > 100); // the raw picture must be sorta big
  /external/brotli/enc/
backward_references.c 29 size_t offset0 = distance_plus_3 - (size_t)dist_cache[0]; local
35 } else if (offset0 < 7) {
36 return (0x9750468 >> (4 * offset0)) & 0xF;
  /external/llvm/test/CodeGen/AMDGPU/
ds_read2_offset_order.ll 7 ; offset0 is larger than offset1
11 ; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:2 offset1:3
12 ; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:14 offset1:12
dagcombine-reassociate-bug.ll 16 %offset0 = add i64 %offset, 1027
17 %ptr0 = getelementptr i32, i32 addrspace(1)* %out, i64 %offset0
load-local-i16.ll 54 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}}
68 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
69 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}}
242 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1 offset1:2{{$}}
259 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:1{{$}}
270 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3
271 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5
272 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7
281 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1 offset1:2{{$}}
282 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:
    [all...]
load-local-i32.ll 39 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}}
49 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
50 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}}
59 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:4{{$}}
60 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:5 offset1:6{{$}}
61 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7{{$}}
62 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1 offset1:2{{$}}
local-64.ll 125 ; BOTH: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:15 offset1:14
135 ; BOTH: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:1
144 ; BOTH-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:31 offset1:30
145 ; BOTH-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:29 offset1:28
155 ; BOTH-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:3 offset1:2
156 ; BOTH-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:1
reduce-store-width-alignment.ll 14 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3
33 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3
scratch-buffer.ll 60 %offset0 = load i32, i32 addrspace(1)* %offsets
61 %scratchptr0 = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %offset0
62 store i32 %offset0, i32* %scratchptr0
ds_read2_superreg.ll 40 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_Z:[0-9]+]]:[[REG_W:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
115 ; CI-DAG: ds_read2_b64 [[VEC_HI:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}}
132 ; CI-DAG: ds_read2_b64 [[VEC4_7:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}}
133 ; CI-DAG: ds_read2_b64 [[VEC8_11:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:4 offset1:5{{$}}
134 ; CI-DAG: ds_read2_b64 [[VEC12_15:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:6 offset1:7{{$}}
175 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT2:[0-9]+]]:[[REG_ELT3:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
  /external/skia/src/utils/
SkInsetConvexPolygon.h 49 * @param offset0 First endpoint of offset segment.
54 int side, SkPoint* offset0, SkPoint* offset1);
SkInsetConvexPolygon.cpp 54 int side, SkPoint* offset0, SkPoint* offset1) {
60 *offset0 = p0 + perp;
80 offset0->fX = p0.fX + (d0sq*dP.fX - side*d0*dP.fY*discrim) / dPlenSq;
81 offset0->fY = p0.fY + (d0sq*dP.fY + side*d0*dP.fX*discrim) / dPlenSq;
  /external/mesa3d/src/egl/wayland/wayland-drm/
wayland-drm.c 76 int32_t offset0, int32_t stride0,
93 buffer->offset[0] = offset0;
148 int32_t offset0, int32_t stride0,
169 offset0, stride0, offset1, stride1, offset2, stride2);
177 int32_t offset0, int32_t stride0,
182 offset0, stride0, offset1, stride1, offset2, stride2);
  /external/llvm/lib/Target/AMDGPU/
SILoadStoreOptimizer.cpp 15 // ds_read2_b32 v[0:1], v2, offset0:4 offset1:8
65 static bool offsetsCanBeCombined(unsigned Offset0,
130 bool SILoadStoreOptimizer::offsetsCanBeCombined(unsigned Offset0,
135 if (Offset0 == Offset1)
139 if ((Offset0 % Size != 0) || (Offset1 % Size != 0))
142 unsigned EltOffset0 = Offset0 / Size;
181 unsigned Offset0 = I->getOperand(OffsetIdx).getImm() & 0xffff;
185 if (offsetsCanBeCombined(Offset0, Offset1, EltSize))
205 unsigned Offset0
210 unsigned NewOffset0 = Offset0 / EltSize
    [all...]
AMDGPUInstrInfo.cpp 51 int64_t Offset0, int64_t Offset1,
53 assert(Offset1 > Offset0 &&
59 return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
  /external/llvm/test/CodeGen/Mips/
eh-return32.ll 18 ; CHECK: sw $4, [[offset0:[0-9]+]]($sp)
36 ; CHECK: lw $4, [[offset0]]($sp)
60 ; CHECK: sw $4, [[offset0:[0-9]+]]($sp)
76 ; CHECK: lw $4, [[offset0]]($sp)
eh-return64.ll 19 ; CHECK: sd $4, [[offset0:[0-9]+]]($sp)
37 ; CHECK: ld $4, [[offset0]]($sp)
63 ; CHECK: sd $4, [[offset0:[0-9]+]]($sp)
79 ; CHECK: ld $4, [[offset0]]($sp)
  /external/llvm/test/Analysis/Delinearization/
multidim_ivs_and_integer_offsets_3d.ll 30 %offset0 = add nsw i64 %i, 3
31 %subscript0 = mul i64 %offset0, %m
multidim_ivs_and_parameteric_offsets_3d.ll 30 %offset0 = add nsw i64 %i, %p
31 %subscript0 = mul i64 %offset0, %m
  /external/llvm/test/Transforms/LoopVectorize/
pr25281.ll 31 %offset0 = add i32 %tmp6, %channelIndex
32 %tmp7 = getelementptr float, float* %in_0, i32 %offset0
  /hardware/intel/common/libva/va/wayland/
wayland-drm-client-protocol.h 194 wl_drm_create_planar_buffer(struct wl_drm *wl_drm, uint32_t name, int32_t width, int32_t height, uint32_t format, int32_t offset0, int32_t stride0, int32_t offset1, int32_t stride1, int32_t offset2, int32_t stride2)
204 WL_DRM_CREATE_PLANAR_BUFFER, id, name, width, height, format, offset0, stride0, offset1, stride1, offset2, stride2);

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