| /external/vixl/test/aarch32/traces/ |
| assembler-cond-rd-rn-operand-rm-a32-orrs.h | 38 0x0e, 0x40, 0x95, 0xd1 // orrs le r4 r5 r14
41 0x0a, 0x50, 0x9b, 0xa1 // orrs ge r5 r11 r10
44 0x09, 0x00, 0x99, 0x91 // orrs ls r0 r9 r9
47 0x02, 0x80, 0x97, 0xd1 // orrs le r8 r7 r2
50 0x0d, 0x10, 0x9a, 0x01 // orrs eq r1 r10 r13
53 0x02, 0x90, 0x9c, 0xd1 // orrs le r9 r12 r2
56 0x05, 0x60, 0x91, 0x51 // orrs pl r6 r1 r5
59 0x06, 0x10, 0x9c, 0xa1 // orrs ge r1 r12 r6
62 0x03, 0xd0, 0x9c, 0x31 // orrs cc r13 r12 r3
65 0x09, 0x20, 0x94, 0xc1 // orrs gt r2 r4 r
[all...] |
| assembler-cond-rd-rn-operand-rm-t32-orrs.h | 38 0x59, 0xea, 0x0b, 0x0c // orrs al r12 r9 r11
41 0x54, 0xea, 0x0a, 0x03 // orrs al r3 r4 r10
44 0x50, 0xea, 0x0c, 0x02 // orrs al r2 r0 r12
47 0x59, 0xea, 0x0d, 0x09 // orrs al r9 r9 r13
50 0x52, 0xea, 0x04, 0x0b // orrs al r11 r2 r4
53 0x53, 0xea, 0x07, 0x07 // orrs al r7 r3 r7
56 0x56, 0xea, 0x09, 0x0b // orrs al r11 r6 r9
59 0x57, 0xea, 0x0b, 0x08 // orrs al r8 r7 r11
62 0x5c, 0xea, 0x0e, 0x0e // orrs al r14 r12 r14
65 0x55, 0xea, 0x08, 0x08 // orrs al r8 r5 r
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-rs-a32-orrs.h | 38 0x1a, 0x6c, 0x98, 0xe1 // orrs al r6 r8 r10 LSL r12
41 0x16, 0x54, 0x9d, 0x81 // orrs hi r5 r13 r6 LSL r4
44 0x7e, 0xb1, 0x90, 0x61 // orrs vs r11 r0 r14 ROR r1
47 0x7b, 0x54, 0x90, 0x71 // orrs vc r5 r0 r11 ROR r4
50 0x16, 0x91, 0x97, 0x01 // orrs eq r9 r7 r6 LSL r1
53 0x3c, 0xc0, 0x99, 0x21 // orrs cs r12 r9 r12 LSR r0
56 0x5d, 0xc3, 0x93, 0x41 // orrs mi r12 r3 r13 ASR r3
59 0x30, 0xd1, 0x94, 0x61 // orrs vs r13 r4 r0 LSR r1
62 0x13, 0x3d, 0x97, 0x31 // orrs cc r3 r7 r3 LSL r13
65 0x11, 0xa6, 0x91, 0xd1 // orrs le r10 r1 r1 LSL r
[all...] |
| assembler-cond-rd-rn-operand-const-a32-orrs.h | 38 0xff, 0x97, 0x94, 0xd3 // orrs le r9 r4 0x03fc0000
41 0xff, 0xeb, 0x93, 0x53 // orrs pl r14 r3 0x0003fc00
44 0xff, 0x15, 0x96, 0x33 // orrs cc r1 r6 0x3fc00000
47 0xab, 0x57, 0x91, 0x33 // orrs cc r5 r1 0x02ac0000
50 0xab, 0xe2, 0x94, 0x53 // orrs pl r14 r4 0xb000000a
53 0xff, 0x2b, 0x9d, 0x23 // orrs cs r2 r13 0x0003fc00
56 0xab, 0xd5, 0x90, 0x43 // orrs mi r13 r0 0x2ac00000
59 0xff, 0x0a, 0x90, 0x73 // orrs vc r0 r0 0x000ff000
62 0xff, 0x2e, 0x99, 0x63 // orrs vs r2 r9 0x00000ff0
65 0xff, 0xf0, 0x97, 0x33 // orrs cc r15 r7 0x000000f
[all...] |
| assembler-cond-rd-rn-operand-const-t32-orrs.h | 38 0x5e, 0xf0, 0x2b, 0x7d // orrs al r13 r14 0x02ac0000
41 0x51, 0xf4, 0xab, 0x1a // orrs al r10 r1 0x00156000
44 0x50, 0xf4, 0x7f, 0x7a // orrs al r10 r0 0x000003fc
47 0x5b, 0xf0, 0x2b, 0x51 // orrs al r1 r11 0x2ac00000
50 0x56, 0xf4, 0xab, 0x18 // orrs al r8 r6 0x00156000
53 0x5c, 0xf4, 0x7f, 0x07 // orrs al r7 r12 0x00ff0000
56 0x53, 0xf4, 0x7f, 0x0c // orrs al r12 r3 0x00ff0000
59 0x57, 0xf4, 0x7f, 0x44 // orrs al r4 r7 0x0000ff00
62 0x5d, 0xf0, 0x2b, 0x6b // orrs al r11 r13 0x0ab00000
65 0x5c, 0xf0, 0xff, 0x26 // orrs al r6 r12 0xff00ff0
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-orrs.h | 38 0x80, 0xd2, 0x9d, 0x01 // orrs eq r13 r13 r0 LSL 5
41 0x0d, 0xa5, 0x9e, 0x41 // orrs mi r10 r14 r13 LSL 10
44 0x0d, 0x62, 0x92, 0x81 // orrs hi r6 r2 r13 LSL 4
47 0x0d, 0x31, 0x95, 0xa1 // orrs ge r3 r5 r13 LSL 2
50 0x61, 0xa5, 0x95, 0x31 // orrs cc r10 r5 r1 ROR 10
53 0xe7, 0x33, 0x9e, 0xa1 // orrs ge r3 r14 r7 ROR 7
56 0x87, 0xbb, 0x91, 0x51 // orrs pl r11 r1 r7 LSL 23
59 0x84, 0x8a, 0x96, 0xd1 // orrs le r8 r6 r4 LSL 21
62 0x82, 0x21, 0x99, 0x11 // orrs ne r2 r9 r2 LSL 3
65 0x08, 0xe2, 0x9e, 0xa1 // orrs ge r14 r14 r8 LSL
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-orrs.h | 38 0x54, 0xea, 0xc7, 0x1c // orrs al r12 r4 r7 LSL 7
41 0x58, 0xea, 0x7a, 0x57 // orrs al r7 r8 r10 ROR 21
44 0x55, 0xea, 0x33, 0x35 // orrs al r5 r5 r3 ROR 12
47 0x5d, 0xea, 0x8a, 0x5e // orrs al r14 r13 r10 LSL 22
50 0x5a, 0xea, 0xbb, 0x09 // orrs al r9 r10 r11 ROR 2
53 0x5b, 0xea, 0xc5, 0x3e // orrs al r14 r11 r5 LSL 15
56 0x52, 0xea, 0x07, 0x72 // orrs al r2 r2 r7 LSL 28
59 0x5b, 0xea, 0x71, 0x22 // orrs al r2 r11 r1 ROR 9
62 0x52, 0xea, 0x08, 0x1b // orrs al r11 r2 r8 LSL 4
65 0x5d, 0xea, 0x73, 0x06 // orrs al r6 r13 r3 ROR
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-orrs.h | 38 0xc7, 0xd2, 0x96, 0x01 // orrs eq r13 r6 r7 ASR 5
41 0x48, 0x80, 0x9b, 0x41 // orrs mi r8 r11 r8 ASR 32
44 0x4a, 0x29, 0x93, 0x81 // orrs hi r2 r3 r10 ASR 18
47 0x2e, 0xd0, 0x98, 0x91 // orrs ls r13 r8 r14 LSR 32
50 0xc2, 0x81, 0x99, 0x31 // orrs cc r8 r9 r2 ASR 3
53 0x25, 0xe1, 0x92, 0x91 // orrs ls r14 r2 r5 LSR 2
56 0xc1, 0x8f, 0x96, 0x51 // orrs pl r8 r6 r1 ASR 31
59 0xae, 0x21, 0x90, 0xd1 // orrs le r2 r0 r14 LSR 3
62 0xad, 0x27, 0x90, 0x11 // orrs ne r2 r0 r13 LSR 15
65 0x23, 0x94, 0x9c, 0xa1 // orrs ge r9 r12 r3 LSR
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-orrs.h | 38 0x5d, 0xea, 0x6a, 0x2b // orrs al r11 r13 r10 ASR 9
41 0x55, 0xea, 0xa2, 0x07 // orrs al r7 r5 r2 ASR 2
44 0x52, 0xea, 0x5b, 0x15 // orrs al r5 r2 r11 LSR 5
47 0x56, 0xea, 0x1a, 0x0e // orrs al r14 r6 r10 LSR 32
50 0x56, 0xea, 0x53, 0x39 // orrs al r9 r6 r3 LSR 13
53 0x54, 0xea, 0xd6, 0x7e // orrs al r14 r4 r6 LSR 31
56 0x51, 0xea, 0x97, 0x32 // orrs al r2 r1 r7 LSR 14
59 0x59, 0xea, 0x1c, 0x62 // orrs al r2 r9 r12 LSR 24
62 0x5c, 0xea, 0xa4, 0x0a // orrs al r10 r12 r4 ASR 2
65 0x5a, 0xea, 0x10, 0x26 // orrs al r6 r10 r0 LSR
[all...] |
| /art/runtime/interpreter/mterp/arm/ |
| op_goto_32.S | 15 orrs rINST, r0, r3, lsl #16 @ rINST<- AAAAaaaa
|
| op_double_to_long.S | 29 orrs r3, r0, r1, lsl #12
|
| binopWide.S | 28 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
|
| binopWide2addr.S | 24 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| tcompat2.d | 19 0+10 <[^>]*> 4308 * orrs r0, r1
20 0+12 <[^>]*> 4308 * orrs r0, r1
|
| armv1.s | 21 orrs r0, r0, r0
|
| thumb2_it.s | 23 orrs r0, r0, r2
|
| /external/llvm/test/MC/ARM/ |
| thumb_rewrites.s | 92 orrs r0, r0, r1
93 @ CHECK: orrs r0, r1 @ encoding: [0x08,0x43]
95 orrs r0, r1, r0
96 @ CHECK: orrs r0, r1 @ encoding: [0x08,0x43]
|
| /external/llvm/test/CodeGen/ARM/ |
| 2011-04-15-RegisterCmpPeephole.ll | 23 ; CHECK: orrs
|
| fast-isel-binary.ll | 52 ; THUMB: orrs r0, r1
64 ; THUMB: orrs r0, r1
76 ; THUMB: orrs r0, r1
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| 2011-04-15-RegisterCmpPeephole.ll | 23 ; CHECK: orrs
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
| thumb2-orr.ll | 5 ; CHECK: orrs r0, r1
|
| /device/google/contexthub/firmware/os/cpu/cortexm4/ |
| atomicBitset.c | 75 " orrs %0, %3 \n"
99 " orrs %0, %3 \n"
|
| /external/vixl/test/aarch32/config/ |
| cond-rd-rn-operand-const-a32.json | 43 "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
|
| cond-rd-rn-operand-const-t32.json | 51 "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
|
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-orr.ll | 5 ; CHECK: orrs r0, r1
|
