| /external/llvm/test/CodeGen/X86/ |
| pr20088.ll | 3 declare <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8>, <16 x i8>, <16 x i8>)
7 %res = call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> zeroinitializer, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8> %x)
|
| vec_shift4.ll | 42 ; X32-NEXT: pblendvb %xmm3, %xmm2
48 ; X32-NEXT: pblendvb %xmm3, %xmm2
53 ; X32-NEXT: pblendvb %xmm3, %xmm2
65 ; X64-NEXT: pblendvb %xmm3, %xmm2
71 ; X64-NEXT: pblendvb %xmm3, %xmm2
76 ; X64-NEXT: pblendvb %xmm3, %xmm2
81 ; CHECK: pblendvb
82 ; CHECK: pblendvb
83 ; CHECK: pblendvb
|
| 2011-12-28-vselecti8.ll | 14 ; don't generate psll, psraw and pblendvb from the vselect.
19 ; CHECK-NOT: pblendvb
|
| 2011-12-15-vec_shift.ll | 10 ; CHECK-W-SSE4: pblendvb [[REG1]],{{ %xmm.}}
|
| 2011-11-30-or.ll | 8 ; CHECK: pblendvb {{LCPI0_[0-9]*}}(%rip), %xmm1
|
| vector-shift-shl-128.ll | 197 ; SSE41-NEXT: pblendvb %xmm4, %xmm2
201 ; SSE41-NEXT: pblendvb %xmm1, %xmm2
206 ; SSE41-NEXT: pblendvb %xmm1, %xmm2
211 ; SSE41-NEXT: pblendvb %xmm1, %xmm2
334 ; SSE41-NEXT: pblendvb %xmm3, %xmm2
340 ; SSE41-NEXT: pblendvb %xmm3, %xmm2
345 ; SSE41-NEXT: pblendvb %xmm3, %xmm2
594 ; SSE41-NEXT: pblendvb %xmm4, %xmm2
599 ; SSE41-NEXT: pblendvb %xmm1, %xmm2
604 ; SSE41-NEXT: pblendvb %xmm1, %xmm
[all...] |
| vector-rotate-128.ll | 341 ; SSE41-NEXT: pblendvb %xmm6, %xmm5
345 ; SSE41-NEXT: pblendvb %xmm1, %xmm5
350 ; SSE41-NEXT: pblendvb %xmm1, %xmm5
355 ; SSE41-NEXT: pblendvb %xmm1, %xmm5
365 ; SSE41-NEXT: pblendvb %xmm4, %xmm3
369 ; SSE41-NEXT: pblendvb %xmm2, %xmm3
374 ; SSE41-NEXT: pblendvb %xmm2, %xmm3
379 ; SSE41-NEXT: pblendvb %xmm2, %xmm3
590 ; SSE41-NEXT: pblendvb %xmm5, %xmm4
596 ; SSE41-NEXT: pblendvb %xmm5, %xmm
[all...] |
| vector-shift-ashr-128.ll | 271 ; SSE41-NEXT: pblendvb %xmm4, %xmm2
275 ; SSE41-NEXT: pblendvb %xmm1, %xmm2
280 ; SSE41-NEXT: pblendvb %xmm1, %xmm2
285 ; SSE41-NEXT: pblendvb %xmm1, %xmm2
438 ; SSE41-NEXT: pblendvb %xmm4, %xmm3
442 ; SSE41-NEXT: pblendvb %xmm4, %xmm3
446 ; SSE41-NEXT: pblendvb %xmm4, %xmm3
452 ; SSE41-NEXT: pblendvb %xmm2, %xmm1
456 ; SSE41-NEXT: pblendvb %xmm2, %xmm1
460 ; SSE41-NEXT: pblendvb %xmm2, %xmm
[all...] |
| vector-shift-lshr-128.ll | 240 ; SSE41-NEXT: pblendvb %xmm4, %xmm2
244 ; SSE41-NEXT: pblendvb %xmm1, %xmm2
249 ; SSE41-NEXT: pblendvb %xmm1, %xmm2
254 ; SSE41-NEXT: pblendvb %xmm1, %xmm2
380 ; SSE41-NEXT: pblendvb %xmm3, %xmm2
386 ; SSE41-NEXT: pblendvb %xmm3, %xmm2
392 ; SSE41-NEXT: pblendvb %xmm3, %xmm2
647 ; SSE41-NEXT: pblendvb %xmm4, %xmm2
652 ; SSE41-NEXT: pblendvb %xmm1, %xmm2
658 ; SSE41-NEXT: pblendvb %xmm1, %xmm
[all...] |
| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| vec_shift4.ll | 19 ; CHECK: pblendvb
20 ; CHECK: pblendvb
21 ; CHECK: pblendvb
|
| vec-sign.ll | 21 ; CHECK: pblendvb
|
| sse41-blend.ll | 57 ;CHECK: pblendvb
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| sse4_1.s | 30 pblendvb %xmm0,(%ecx),%xmm0
31 pblendvb %xmm0,%xmm1,%xmm0
32 pblendvb (%ecx),%xmm0
33 pblendvb %xmm1,%xmm0
127 pblendvb xmm0,XMMWORD PTR [ecx],xmm0
128 pblendvb xmm0,xmm1,xmm0
|
| x86-64-sse4_1.s | 31 pblendvb %xmm0,(%rcx),%xmm0
32 pblendvb %xmm0,%xmm1,%xmm0
33 pblendvb (%rcx),%xmm0
34 pblendvb %xmm1,%xmm0
136 pblendvb xmm0,XMMWORD PTR [rcx],xmm0
137 pblendvb xmm0,xmm1,xmm0
|
| x86-64-specific-reg.s | 89 pblendvb %xmm\n, %xmm\n, %xmm\n
|
| sse4_1-intel.d | 35 [ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb xmm0,XMMWORD PTR \[ecx\](,xmm0)?
36 [ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb xmm0,xmm1(,xmm0)?
37 [ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb xmm0,XMMWORD PTR \[ecx\](,xmm0)?
38 [ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb xmm0,xmm1(,xmm0)?
130 [ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb xmm0,XMMWORD PTR \[ecx\],xmm0
131 [ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb xmm0,xmm1,xmm0
|
| sse4_1.d | 34 [ ]*[0-9a-f]+: 66 0f 38 10 01 pblendvb (%xmm0,)?\(%ecx\),%xmm0
35 [ ]*[0-9a-f]+: 66 0f 38 10 c1 pblendvb (%xmm0,)?%xmm1,%xmm0
36 [ ]*[0-9a-f]+: 66 0f 38 10 01 pblendvb (%xmm0,)?\(%ecx\),%xmm0
37 [ ]*[0-9a-f]+: 66 0f 38 10 c1 pblendvb (%xmm0,)?%xmm1,%xmm0
129 [ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb %xmm0,\(%ecx\),%xmm0
130 [ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb %xmm0,%xmm1,%xmm0
|
| x86-64-sse4_1-intel.d | 36 [ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb xmm0,XMMWORD PTR \[rcx\],xmm0
37 [ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb xmm0,xmm1,xmm0
38 [ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb xmm0,XMMWORD PTR \[rcx\],xmm0
39 [ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb xmm0,xmm1,xmm0
139 [ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb xmm0,XMMWORD PTR \[rcx\],xmm0
140 [ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb xmm0,xmm1,xmm0
|
| x86-64-sse4_1.d | 35 [ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb %xmm0,\(%rcx\),%xmm0
36 [ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb %xmm0,%xmm1,%xmm0
37 [ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb %xmm0,\(%rcx\),%xmm0
38 [ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb %xmm0,%xmm1,%xmm0
138 [ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb %xmm0,\(%rcx\),%xmm0
139 [ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb %xmm0,%xmm1,%xmm0
|
| sse2avx.s | 414 pblendvb %xmm0,%xmm4,%xmm6
415 pblendvb %xmm0,(%ecx),%xmm6
416 pblendvb %xmm4,%xmm6
417 pblendvb (%ecx),%xmm6
1075 pblendvb xmm6,xmm4,xmm0
1076 pblendvb xmm6,XMMWORD PTR [ecx],xmm0
1077 pblendvb xmm6,xmm4
1078 pblendvb xmm6,XMMWORD PTR [ecx]
|
| x86-64-sse2avx.s | 414 pblendvb %xmm0,%xmm4,%xmm6
415 pblendvb %xmm0,(%rcx),%xmm6
416 pblendvb %xmm4,%xmm6
417 pblendvb (%rcx),%xmm6
1118 pblendvb xmm6,xmm4,xmm0
1119 pblendvb xmm6,XMMWORD PTR [rcx],xmm0
1120 pblendvb xmm6,xmm4
1121 pblendvb xmm6,XMMWORD PTR [rcx]
|
| /external/llvm/test/Transforms/InstCombine/ |
| blend_x86.ll | 51 %1 = tail call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %xyzw, <16 x i8> %abcd, <16 x i8> <i8 0, i8 0, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0>)
58 %1 = tail call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %xyzw, <16 x i8> %abcd, <16 x i8> zeroinitializer)
65 %1 = tail call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %xyzw, <16 x i8> %xyzw, <16 x i8> %sel)
117 %1 = tail call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %xyzw, <32 x i8> %abcd,
128 %1 = tail call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %xyzw, <32 x i8> %abcd, <32 x i8> zeroinitializer)
135 %1 = tail call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %xyzw, <32 x i8> %xyzw, <32 x i8> %sel)
139 declare <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8>, <16 x i8>, <16 x i8>)
143 declare <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8>, <32 x i8>, <32 x i8>)
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ilp32/ |
| x86-64-sse4_1-intel.d | 36 [ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb xmm0,XMMWORD PTR \[rcx\],xmm0
37 [ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb xmm0,xmm1,xmm0
38 [ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb xmm0,XMMWORD PTR \[rcx\],xmm0
39 [ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb xmm0,xmm1,xmm0
139 [ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb xmm0,XMMWORD PTR \[rcx\],xmm0
140 [ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb xmm0,xmm1,xmm0
|
| x86-64-sse4_1.d | 36 [ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb %xmm0,\(%rcx\),%xmm0
37 [ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb %xmm0,%xmm1,%xmm0
38 [ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb %xmm0,\(%rcx\),%xmm0
39 [ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb %xmm0,%xmm1,%xmm0
139 [ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb %xmm0,\(%rcx\),%xmm0
140 [ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb %xmm0,%xmm1,%xmm0
|
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_logic.c | 377 intrinsic = "llvm.x86.avx2.pblendvb";
390 intrinsic = "llvm.x86.sse41.pblendvb";
|
