/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
reg.s | 5 psrlw $2, %mm6 label 6 psrlw $2, %xmm6 label 25 psrlw mm6, 2 label 26 psrlw xmm6, 2 label
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x86-64-reg.s | 5 psrlw $2, %mm6 label 6 psrlw $2, %xmm10 label 25 psrlw mm6, 2 label 26 psrlw xmm2, 2 label
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reg-intel.d | 11 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2 12 [ ]*[a-f0-9]+: 66 0f 71 d6 02 psrlw xmm6,0x2 29 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2 30 [ ]*[a-f0-9]+: 66 0f 71 d6 02 psrlw xmm6,0x2
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x86-64-reg-intel.d | 11 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2 12 [ ]*[a-f0-9]+: 66 41 0f 71 d2 02 psrlw xmm10,0x2 29 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2 30 [ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw xmm2,0x2
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reg.d | 9 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw \$0x2,%mm6 10 [ ]*[a-f0-9]+: 66 0f 71 d6 02 psrlw \$0x2,%xmm6 27 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw \$0x2,%mm6 28 [ ]*[a-f0-9]+: 66 0f 71 d6 02 psrlw \$0x2,%xmm6
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x86-64-reg.d | 10 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw \$0x2,%mm6 11 [ ]*[a-f0-9]+: 66 41 0f 71 d2 02 psrlw \$0x2,%xmm10 28 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw \$0x2,%mm6 29 [ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw \$0x2,%xmm2
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/external/llvm/test/CodeGen/X86/ |
2007-03-24-InlineAsmXConstraint.ll | 8 ; CHECK: psrlw $8, %xmm0 11 tail call void asm sideeffect "psrlw $0, %xmm0", "X,~{dirflag},~{fpsr},~{flags}"( i32 8 )
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2012-02-23-mmx-inlineasm.ll | 5 ; CHECK: psrlw %mm0, %mm1 7 call void asm sideeffect "psrlw $0, %mm1", "y,~{dirflag},~{fpsr},~{flags}"(i32 8) nounwind
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pr16807.ll | 11 ; CHECK: psrlw 15 ; CHECK: psrlw
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vector-popcnt-128.ll | 60 ; SSSE3-NEXT: psrlw $4, %xmm0 76 ; SSE41-NEXT: psrlw $4, %xmm0 162 ; SSSE3-NEXT: psrlw $4, %xmm0 184 ; SSE41-NEXT: psrlw $4, %xmm0 223 ; SSE2-NEXT: psrlw $1, %xmm1 229 ; SSE2-NEXT: psrlw $2, %xmm0 233 ; SSE2-NEXT: psrlw $4, %xmm1 239 ; SSE2-NEXT: psrlw $8, %xmm0 245 ; SSE3-NEXT: psrlw $1, %xmm1 251 ; SSE3-NEXT: psrlw $2, %xmm [all...] |
vec_shift2.ll | 10 ; X32-NEXT: psrlw %xmm1, %xmm0 17 ; X64-NEXT: psrlw %xmm1, %xmm0
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lower-vec-shift.ll | 16 ; SSE: psrlw 17 ; SSE-NEXT: psrlw 33 ; SSE: psrlw 34 ; SSE-NEXT: psrlw
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/external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
2007-03-24-InlineAsmXConstraint.ll | 8 ; CHECK: psrlw $8, %xmm0
11 tail call void asm sideeffect "psrlw $0, %xmm0", "X,~{dirflag},~{fpsr},~{flags}"( i32 8 )
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/external/mesa3d/src/mesa/x86/ |
mmx_blend.S | 32 PSRLW ( CONST(8), MA1 ) /* t1 >> 8 ~= t1/255 */ ;\ 33 TWO(PSRLW ( CONST(8), MA2 )) /* t2 >> 8 ~= t2/255 */ 54 PSRLW ( CONST(8), MA1 ) /* t1 >> 8 */ ;\ 57 TWO(PSRLW ( CONST(8), MA2 )) /* t2 >> 8 */ ;\ 60 PSRLW ( CONST(8), MA1 ) /* sa1 | sb1 | sg1 | sr1 */ ;\ 63 TWO(PSRLW ( CONST(8), MA2 )) /* sa2 | sb2 | sg2 | sr2 */ 85 PSRLW ( CONST(8), MA1 ) /* t1 >> 8 */ ;\ 88 TWO(PSRLW ( CONST(8), MA2 )) /* t2 >> 8 */ ;\ 91 PSRLW ( CONST(8), MA1 ) /* sa1 | sb1 | sg1 | sr1 */ ;\ 94 TWO(PSRLW ( CONST(8), MA2 )) /* sa2 | sb2 | sg2 | sr2 * [all...] |
/external/libjpeg-turbo/simd/ |
jcsample-mmx.asm | 103 psrlw mm6,BYTE_BIT ; mm6={0xFF 0x00 0xFF 0x00 ..} 124 psrlw mm2,BYTE_BIT 126 psrlw mm3,BYTE_BIT 132 psrlw mm0,1 133 psrlw mm1,1 245 psrlw mm6,BYTE_BIT ; mm6={0xFF 0x00 0xFF 0x00 ..} 269 psrlw mm4,BYTE_BIT 271 psrlw mm5,BYTE_BIT 278 psrlw mm4,BYTE_BIT 280 psrlw mm5,BYTE_BI [all...] |
jcsample-sse2-64.asm | 100 psrlw xmm6,BYTE_BIT ; xmm6={0xFF 0x00 0xFF 0x00 ..} 130 psrlw xmm2,BYTE_BIT 132 psrlw xmm3,BYTE_BIT 138 psrlw xmm0,1 139 psrlw xmm1,1 244 psrlw xmm6,BYTE_BIT ; xmm6={0xFF 0x00 0xFF 0x00 ..} 278 psrlw xmm4,BYTE_BIT 280 psrlw xmm5,BYTE_BIT 287 psrlw xmm4,BYTE_BIT 289 psrlw xmm5,BYTE_BI [all...] |
jcsample-sse2.asm | 103 psrlw xmm6,BYTE_BIT ; xmm6={0xFF 0x00 0xFF 0x00 ..} 136 psrlw xmm2,BYTE_BIT 138 psrlw xmm3,BYTE_BIT 144 psrlw xmm0,1 145 psrlw xmm1,1 258 psrlw xmm6,BYTE_BIT ; xmm6={0xFF 0x00 0xFF 0x00 ..} 295 psrlw xmm4,BYTE_BIT 297 psrlw xmm5,BYTE_BIT 304 psrlw xmm4,BYTE_BIT 306 psrlw xmm5,BYTE_BI [all...] |
/external/libvpx/libvpx/vp9/encoder/x86/ |
vp9_quantize_ssse3_x86_64.asm | 38 psrlw m5, 15 40 psrlw m1, 1 ; m1 = (m1 + 1) / 2 82 psrlw m8, 1 83 psrlw m13, 1 86 psrlw m0, m3, 2 88 psrlw m0, m3, 1 135 psrlw m14, 1 136 psrlw m13, 1
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ilp32/ |
x86-64-reg-intel.d | 11 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2 12 [ ]*[a-f0-9]+: 66 41 0f 71 d2 02 psrlw xmm10,0x2 29 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2 30 [ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw xmm2,0x2
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x86-64-reg.d | 11 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw \$0x2,%mm6 12 [ ]*[a-f0-9]+: 66 41 0f 71 d2 02 psrlw \$0x2,%xmm10 29 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw \$0x2,%mm6 30 [ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw \$0x2,%xmm2
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/external/libvpx/libvpx/vpx_dsp/x86/ |
highbd_subpel_variance_impl_sse2.asm | 336 psrlw m1, 4 337 psrlw m0, 4 364 psrlw m1, 4 365 psrlw m0, 4 566 psrlw m1, 4 569 psrlw m0, 4 605 psrlw m4, 4 608 psrlw m0, 4 680 psrlw m1, 4 681 psrlw m0, [all...] |
quantize_ssse3_x86_64.asm | 38 psrlw m5, 15 41 psrlw m0, 1 ; m0 = (m0 + 1) / 2 42 psrlw m1, 1 ; m1 = (m1 + 1) / 2 129 psrlw m8, 1 130 psrlw m13, 1 230 psrlw m14, 1 231 psrlw m13, 1
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/external/libvpx/libvpx/vp8/encoder/x86/ |
quantize_mmx.asm | 214 psrlw mm0, 15 216 psrlw mm1, 15 237 psrlw mm0, 15 239 psrlw mm1, 15
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/external/libvpx/libvpx/third_party/libyuv/source/ |
scale_win.cc | 110 psrlw xmm0, 8 // isolate odd pixels. 111 psrlw xmm1, 8 133 psrlw xmm4, 15 167 psrlw xmm4, 15 183 psrlw xmm0, 1 184 psrlw xmm1, 1 330 psrlw xmm0, 8 354 psrlw xmm4, 15 385 psrlw xmm0, 4 // /16 for average of 4 * 4 568 psrlw xmm0, [all...] |
/external/libyuv/files/source/ |
scale_win.cc | 105 psrlw xmm0, 8 // isolate odd pixels. 106 psrlw xmm1, 8 129 psrlw xmm4, 15 164 psrlw xmm4, 15 180 psrlw xmm0, 1 181 psrlw xmm1, 1 331 psrlw xmm0, 8 356 psrlw xmm4, 15 387 psrlw xmm0, 4 // /16 for average of 4 * 4 573 psrlw xmm0, [all...] |