| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/ |
| QNCAccess.h | 23 #define EFI_LPC_PCI_ADDRESS( Register ) \
24 EFI_PCI_ADDRESS(PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, Register)
35 #define LpcPciCfg32( Register ) \
36 QNCMmPci32(0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )
38 #define LpcPciCfg32Or( Register, OrData ) \
39 QNCMmPci32Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )
41 #define LpcPciCfg32And( Register, AndData ) \
42 QNCMmPci32And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )
44 #define LpcPciCfg32AndThenOr( Register, AndData, OrData ) \
45 QNCMmPci32AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )
[all...] |
| QNCCommonDefinitions.h | 20 // PCI CONFIGURATION MAP REGISTER OFFSETS
23 #define PCI_VID 0x0000 // Vendor ID Register
24 #define PCI_DID 0x0002 // Device ID Register
25 #define PCI_CMD 0x0004 // PCI Command Register
26 #define PCI_STS 0x0006 // PCI Status Register
27 #define PCI_RID 0x0008 // Revision ID Register
29 #define PCI_SCC 0x000A // Sub Class Code Register
30 #define PCI_BCC 0x000B // Base Class Code Register
33 #define PCI_HDR 0x000E // Header Type Register
34 #define PCI_BIST 0x000F // Built in Self Test Register
[all...] |
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/ |
| VlvAccess.h | 36 #define MmioAddress( BaseAddr, Register ) \
38 (UINTN)(Register) \
46 #define Mmio32Ptr( BaseAddr, Register ) \
47 ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )
49 #define Mmio32( BaseAddr, Register ) \
50 *Mmio32Ptr( BaseAddr, Register )
52 #define Mmio32Or( BaseAddr, Register, OrData ) \
53 Mmio32( BaseAddr, Register ) = \
55 Mmio32( BaseAddr, Register ) | \
59 #define Mmio32And( BaseAddr, Register, AndData ) \
[all...] |
| VlvCommonDefinitions.h | 27 /// PCI CONFIGURATION MAP REGISTER OFFSETS
30 #define PCI_VID 0x0000 ///< Vendor ID Register
31 #define PCI_DID 0x0002 ///< Device ID Register
32 #define PCI_CMD 0x0004 ///< PCI Command Register
33 #define PCI_STS 0x0006 ///< PCI Status Register
34 #define PCI_RID 0x0008 ///< Revision ID Register
36 #define PCI_SCC 0x000A ///< Sub Class Code Register
37 #define PCI_BCC 0x000B ///< Base Class Code Register
40 #define PCI_HDR 0x000E ///< Header Type Register
41 #define PCI_BIST 0x000F ///< Built in Self Test Register
[all...] |
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/ |
| IohCommonDefinitions.h | 20 // PCI CONFIGURATION MAP REGISTER OFFSETS
23 #define PCI_VID 0x0000 // Vendor ID Register
24 #define PCI_DID 0x0002 // Device ID Register
25 #define PCI_CMD 0x0004 // PCI Command Register
26 #define PCI_STS 0x0006 // PCI Status Register
27 #define PCI_RID 0x0008 // Revision ID Register
29 #define PCI_SCC 0x000A // Sub Class Code Register
30 #define PCI_BCC 0x000B // Base Class Code Register
33 #define PCI_HDR 0x000E // Header Type Register
34 #define PCI_BIST 0x000F // Built in Self Test Register
[all...] |
| /external/clang/test/SemaCXX/Inputs/ |
| register.h | 4 inline void f() { register int k; }
5 #define to_int(x) ({ register int n = (x); n; })
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.15-4.8/sysroot/usr/include/X11/ |
| ImUtil.h | 18 register XImage *dstimg,
19 register int x,
20 register int y);
24 register unsigned char *bpt,
25 register int nb);
28 register XImage *image);
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| ldrd-unpredictable.l | 2 [^:]*:6: Warning: index register overlaps transfer register
3 [^:]*:7: Warning: index register overlaps transfer register
4 [^:]*:8: Warning: source register same as write-back base
5 [^:]*:9: Warning: base register written back, and overlaps second transfer register
6 [^:]*:13: Warning: source register same as write-back base
7 [^:]*:14: Warning: base register written back, and overlaps second transfer register
[all...] |
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
| PchCommonDefinitions.h | 30 #define PchMmioAddress(BaseAddr, Register) ((UINTN) BaseAddr + (UINTN) (Register))
35 #define PchMmio32Ptr(BaseAddr, Register) ((volatile UINT32 *) PchMmioAddress (BaseAddr, Register))
37 #define PchMmio32(BaseAddr, Register) *PchMmio32Ptr (BaseAddr, Register)
39 #define PchMmio32Or(BaseAddr, Register, OrData) \
40 PchMmio32 (BaseAddr, Register) = (UINT32) \
41 (PchMmio32 (BaseAddr, Register) | (UINT32) (OrData))
43 #define PchMmio32And(BaseAddr, Register, AndData) \
[all...] |
| PchAccess.h | 44 #define MmPciAddress(Segment, Bus, Device, Function, Register) \
49 (UINTN) (Register) \
66 #define PchAzaliaPciCfg32(Register) \
72 Register) \
75 #define PchAzaliaPciCfg32Or(Register, OrData) \
81 Register), \
85 #define PchAzaliaPciCfg32And(Register, AndData) \
91 Register), \
95 #define PchAzaliaPciCfg32AndThenOr(Register, AndData, OrData) \
101 Register), \
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/d30v/ |
| warn_oddreg.l | 2 .*:5: Warning: Odd numbered register used as target of multi-register instruction
3 .*:6: Warning: Odd numbered register used as target of multi-register instruction
4 .*:7: Warning: Odd numbered register used as target of multi-register instruction
5 .*:8: Warning: Odd numbered register used as target of multi-register instruction
6 .*:9: Warning: Odd numbered register used as target of multi-register instructio
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.8/sysroot/usr/include/X11/ |
| ImUtil.h | 19 register XImage *dstimg,
20 register int x,
21 register int y);
25 register unsigned char *bpt,
26 register int nb);
29 register XImage *image);
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/s390/ |
| zarch-z9-109-err.l | 2 .*:3: Fatal error: odd numbered general purpose register specified as register pair
|
| /external/v8/src/interpreter/ |
| bytecode-register.h | 17 // An interpreter Register which is located in the function's Register file
18 // in its stack-frame. Register hold parameters, this, and expression values.
19 class V8_EXPORT_PRIVATE Register final {
21 explicit Register(int index = kInvalidIndex) : index_(index) {}
27 static Register FromParameterIndex(int index, int parameter_count);
30 // Returns an invalid register.
31 static Register invalid_value() { return Register(); }
33 // Returns the register for the function's closure object
[all...] |
| /art/test/404-optimizing-allocator/ |
| info.txt | 1 Initial tests for testing the optimizing compiler's register allocator.
|
| /art/test/405-optimizing-long-allocator/ |
| info.txt | 1 Tests with long for the optimizing compiler's register allocator.
|
| /art/test/482-checker-loop-back-edge-use/ |
| info.txt | 1 Tests the register allocator's optimization of adding synthesized uses
|
| /art/test/529-long-split/ |
| info.txt | 2 during register allocation.
|
| /art/test/642-fp-callees/ |
| info.txt | 2 use D14 as a temporary register.
|
| /art/test/705-register-conflict/ |
| info.txt | 1 Tests if blocked fp register work correctly on optimizing compiler.
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| legacy_reg_names.d | 1 #name: Legacy register names errors
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/d10v/ |
| warning-001.d | 2 #warning : cr6 is a reserved control register
|
| warning-002.d | 2 #warning : cr6 is a reserved control register
|
| warning-003.d | 2 #warning : cr12 is a reserved control register
|
| warning-004.d | 2 #warning : cr12 is a reserved control register
|
