| /external/clang/test/CodeGen/ |
| BasicInstrs.c | 19 _Bool setlt(int X, int Y) { function
|
| /external/llvm/test/Transforms/InstCombine/ |
| setcc-strength-reduce.ll | 2 ; working. Basically this boils down to converting setlt,gt,le,ge instructions
|
| /external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/ |
| setcc-strength-reduce.ll | 2 ; working. Basically this boils down to converting setlt,gt,le,ge instructions
|
| /external/llvm/test/CodeGen/PowerPC/ |
| ppc-vaarg-agg.ll | 44 ; with an error like: Cannot select: ch = setlt [ID=6]
|
| /external/llvm/test/Transforms/LoopStrengthReduce/ |
| dont-hoist-simple-loop-constants.ll | 4 ; The setlt wants to use a value that is incremented one more than the dominant
|
| /external/swiftshader/third_party/LLVM/test/Transforms/LoopStrengthReduce/ |
| dont-hoist-simple-loop-constants.ll | 4 ; The setlt wants to use a value that is incremented one more than the dominant
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSelectCCInfo.td | 43 IntRegs:$fval, SETLT)),
111 // setlt-64 -> setgt-64.
113 DoubleRegs:$fval, SETLT)),
|
| HexagonInstrInfoVector.td | 306 def: InvertCmp_pat<A4_vcmpbgt, setlt, V8I8, i1>;
307 def: InvertCmp_pat<A4_vcmpbgt, setlt, V8I8, v8i1>;
308 def: InvertCmp_pat<A2_vcmphgt, setlt, V4I16, i1>;
309 def: InvertCmp_pat<A2_vcmphgt, setlt, V4I16, v4i1>;
310 def: InvertCmp_pat<A2_vcmpwgt, setlt, V2I32, i1>;
311 def: InvertCmp_pat<A2_vcmpwgt, setlt, V2I32, v2i1>;
|
| HexagonInstrInfoV5.td | 494 def: Pat<(i1 (setlt F32:$src1, F32:$src2)),
496 def: Pat<(i1 (setlt F32:$src1, fpimm:$src2)),
498 def: Pat<(i1 (setlt F64:$src1, F64:$src2)),
500 def: Pat<(i1 (setlt F64:$src1, fpimm:$src2)),
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyInstrFloat.td | 67 def : Pat<(setlt f32:$lhs, f32:$rhs), (LT_F32 f32:$lhs, f32:$rhs)>;
73 def : Pat<(setlt f64:$lhs, f64:$rhs), (LT_F64 f64:$lhs, f64:$rhs)>;
|
| WebAssemblyInstrInteger.td | 46 defm LT_S : ComparisonInt<SETLT, "lt_s">;
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| Analysis.cpp | 158 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
166 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
192 case ICmpInst::ICMP_SLT: return ISD::SETLT;
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| Mips64InstrInfo.td | 100 def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
108 def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
163 def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
|
| /external/llvm/utils/emacs/ |
| llvm-mode.el | 44 "setne" "seteq" "setlt" "setgt" "setle" "setge") 'symbols) . font-lock-keyword-face)
|
| /external/swiftshader/third_party/LLVM/utils/emacs/ |
| llvm-mode.el | 37 "setne" "seteq" "setlt" "setgt" "setle" "setge") 'words) . font-lock-keyword-face)
|
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/x86/ |
| anames.go | 204 "SETLT",
|
| /prebuilts/go/linux-x86/src/cmd/internal/obj/x86/ |
| anames.go | 204 "SETLT",
|
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.td | [all...] |
| Mips64InstrInfo.td | 104 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
130 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
241 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
543 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPU64InstrInfo.td | 225 // i64 setge/setlt:
253 def : I64SETCCNegCond<setlt, I64GEr64>;
254 def : I64SELECTNegCond<setlt, I64GEr64>;
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaInstrInfo.td | 201 defm CMOVLT : cmov_inst<0x44, "cmovlt", CmpOpFrag<(setlt node:$R, 0)>>;
221 def : Pat<(select (setlt GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
359 [(set GPRC:$RC, (setlt GPRC:$RA, GPRC:$RB))], s_iadd>;
361 [(set GPRC:$RC, (setlt GPRC:$RA, immUExt8:$L))], s_iadd>;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 557 case ISD::SETLT: return PPC::PRED_LT;
584 case ISD::SETLT: return 0; // Bit #0 = SETOLT
637 case ISD::SETLT: {
670 case ISD::SETLT: {
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 350 case ISD::SETLT: return "setlt";
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrQPX.td | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | [all...] |
