| /art/test/451-spill-splot/ |
| info.txt | 2 way it spills intervals of different types.
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| /external/llvm/lib/CodeGen/ |
| InlineSpiller.cpp | 1 //===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
11 // inserting spills and restores in VirtRegMap.
47 STATISTIC(NumSpills, "Number of spills inserted");
48 STATISTIC(NumSpillsRemoved, "Number of spills removed");
77 // Map from pair of (StackSlot and Original VNI) to a set of spills which
79 // These spills are mergeable and are hoist candiates.
93 SmallPtrSet<MachineInstr *, 16> &Spills,
98 MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
105 SmallPtrSet<MachineInstr *, 16> &Spills,
163 // Object records spills information and does the hoisting
[all...] |
| LiveInterval.cpp | 941 // - When LastStart is invalid, Spills is empty and the iterators are invalid.
949 // 3. Spills.
954 // - Segments in Spills precede and can't coalesce with segments in area 2.
955 // - No coalescing is possible between segments in Spills and segments in area
958 // The segments in Spills are not ordered with respect to the segments in area
961 // When they exist, Spills.back().start <= LastStart,
978 OS << "\n Spills:";
979 for (unsigned I = 0, E = Spills.size(); I != E; ++I)
980 OS << ' ' << Spills[I];
[all...] |
| /external/llvm/test/CodeGen/SystemZ/ |
| alias-01.ll | 5 ; Check that there are no spills.
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| /external/llvm/test/CodeGen/X86/ |
| 2003-08-03-CallArgLiveRanges.ll | 5 ; cause spills!
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| sink-cheap-instructions.ll | 2 ; RUN: llc < %s -mtriple=x86_64-linux -sink-insts-to-avoid-spills | FileCheck %s -check-prefix=SINK
5 ; spills.
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| 2008-10-27-CoalescerBug.ll | 3 ; Now this test spills one register. But a reload in the loop is cheaper than
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| x86-32-intrcc.ll | 8 ; Spills eax, putting original esp at +4.
28 ; Spills eax and ecx, putting original esp at +8. Stack is adjusted up another 4 bytes
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| x86-64-intrcc.ll | 8 ; Spills rax, putting original esp at +8.
28 ; Spills rax and rcx, putting original rsp at +16. Stack is adjusted up another 8 bytes
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| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| 2003-08-03-CallArgLiveRanges.ll | 4 ; cause spills!
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| pmul.ll | 23 ; Use a call to force spills.
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| 2008-10-27-CoalescerBug.ll | 2 ; Now this test spills one register. But a reload in the loop is cheaper than
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| /external/llvm/test/CodeGen/Thumb2/ |
| aligned-spill.ll | 1 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=0 | FileCheck %s
2 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=1 | FileCheck %s --check-prefix=NEON
27 ; Stack pointer must be updated before the spills.
32 ; This could legally happen before the spills.
58 ; Stack pointer must be updated before the spills.
85 ; Stack pointer must be updated before the spills.
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| VirtRegRewriter.cpp | 34 STATISTIC(NumPSpills , "Number of physical register spills");
59 ScheduleSpills("schedule-spills",
99 << "(NOTE! Does not include spills and reloads!) ****\n");
419 AvailableSpills &Spills,
438 AvailableSpills &Spills,
446 return GetRegForReload(RC, PhysReg, MF, MI, Spills, MaybeDeadStores,
717 // Available Spills Implementation //
[all...] |
| ShrinkWrapping.cpp | 1 //===-- ShrinkWrapping.cpp - Reduce spills/restores of callee-saved regs --===//
11 // - Spills and restores of callee-saved registers (CSRs) are placed in the
15 // - Avoiding placment of spills/restores in loops: if a CSR is used inside a
16 // loop the spills are placed in the loop preheader, and restores are
27 // which basic blocks require spills and restores for CSRs.
30 // is used to prevent placement of callee-saved register spills/restores
58 STATISTIC(numSRReduced, "Number of CSR spills+restores reduced.");
63 cl::desc("Shrink wrap callee-saved register spills/restores"));
176 /// If shrink wrapping is not being performed, place all spills in
188 dbgs() << "Place CSR spills/restores for
[all...] |
| /external/llvm/test/CodeGen/AMDGPU/ |
| spill-scavenge-offset.ll | 8 ; When the offset of VGPR spills into scratch space gets too large, an additional SGPR
10 ; mechanism works even when many spills happen.
|
| /art/runtime/entrypoints/quick/ |
| quick_trampoline_entrypoints_test.cc | 62 << type << " core spills=" << std::hex << frame_info.CoreSpillMask() << " fp spills="
72 << " core spills=" << std::hex << frame_info.CoreSpillMask()
73 << " fp spills=" << frame_info.FpSpillMask() << std::dec << " ISA " << isa;
|
| /external/llvm/test/CodeGen/SPARC/ |
| spillsize.ll | 6 ; This function spills two values: %p and the materialized large constant.
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| /external/llvm/test/CodeGen/ARM/ |
| gpr-paired-spill-thumbinst.ll | 4 ; This test makes sure spills of 64-bit pairs in Thumb mode actually
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| /external/llvm/test/CodeGen/PowerPC/ |
| frame-size.ll | 11 ; will fail the small-frame-size check and the function has spills).
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| /external/llvm/test/Transforms/SLPVectorizer/AArch64/ |
| load-store-q.ll | 6 ; spills and fills. This is the case for <2 x double>,
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| /art/runtime/arch/x86_64/ |
| jni_entrypoints_x86_64.S | 23 // Save callee and GPR args, mixed together to agree with core spills bitmap.
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| /art/runtime/arch/ |
| arch_test.cc | 73 << type << " core spills=" << std::hex << frame_info.CoreSpillMask() << " fp spills="
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| /external/llvm/lib/Target/Sparc/ |
| SparcSubtarget.h | 126 /// spills and arguments.
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| /external/llvm/test/CodeGen/AArch64/ |
| arm64-zero-cycle-zeroing.ll | 59 ; We used to produce spills+reloads for a Q register with zero cycle zeroing
|
