| /art/runtime/interpreter/mterp/arm64/ |
| op_double_to_float.S | 1 %include "arm64/funopNarrower.S" {"instr":"fcvt s0, d0", "srcreg":"d0", "tgtreg":"s0"}
|
| op_double_to_int.S | 1 %include "arm64/funopNarrower.S" {"instr":"fcvtzs w0, d0", "srcreg":"d0", "tgtreg":"w0"}
|
| op_double_to_long.S | 1 %include "arm64/funopWide.S" {"instr":"fcvtzs x0, d0", "srcreg":"d0", "tgtreg":"x0"}
|
| op_float_to_double.S | 1 %include "arm64/funopWider.S" {"instr":"fcvt d0, s0", "srcreg":"s0", "tgtreg":"d0"}
|
| op_float_to_int.S | 1 %include "arm64/funopNarrow.S" {"instr":"fcvtzs w0, s0", "srcreg":"s0", "tgtreg":"w0"}
|
| op_float_to_long.S | 1 %include "arm64/funopWider.S" {"instr":"fcvtzs x0, s0", "srcreg":"s0", "tgtreg":"x0"}
|
| op_int_to_double.S | 1 %include "arm64/funopWider.S" {"instr":"scvtf d0, w0", "srcreg":"w0", "tgtreg":"d0"}
|
| op_int_to_float.S | 1 %include "arm64/funopNarrow.S" {"instr":"scvtf s0, w0", "srcreg":"w0", "tgtreg":"s0"}
|
| op_long_to_double.S | 1 %include "arm64/funopWide.S" {"instr":"scvtf d0, x0", "srcreg":"x0", "tgtreg":"d0"}
|
| op_long_to_float.S | 1 %include "arm64/funopNarrower.S" {"instr":"scvtf s0, x0", "srcreg":"x0", "tgtreg":"s0"}
|
| funopNarrower.S | 1 %default {"srcreg":"s0", "tgtreg":"d0"}
4 * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg".
11 GET_VREG_WIDE $srcreg, w3
|
| funopWide.S | 1 %default {"srcreg":"s0", "tgtreg":"d0"}
4 * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg".
11 GET_VREG_WIDE $srcreg, w3
|
| funopWider.S | 1 %default {"srcreg":"s0", "tgtreg":"d0"}
4 * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg".
11 GET_VREG $srcreg, w3
|
| funopNarrow.S | 1 %default {"srcreg":"s0", "tgtreg":"d0"}
4 * "instr" line that specifies an instruction that performs "$tgtreg = op $srcreg".
12 GET_VREG $srcreg, w3
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.h | 26 inline static unsigned getCRFromCRBit(unsigned SrcReg) {
28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT |
[all...] |
| /external/mesa3d/src/mesa/program/ |
| prog_opt_constant_fold.c | 39 if (inst->SrcReg[i].File != PROGRAM_CONSTANT)
41 if (inst->SrcReg[i].RelAddr)
140 get_value(prog, &inst->SrcReg[0], a);
141 get_value(prog, &inst->SrcReg[1], b);
149 inst->SrcReg[0] = src_reg_for_vec4(prog, result);
151 inst->SrcReg[1].File = PROGRAM_UNDEFINED;
152 inst->SrcReg[1].Swizzle = SWIZZLE_NOOP;
169 get_value(prog, &inst->SrcReg[0], a);
170 get_value(prog, &inst->SrcReg[1], b);
171 get_value(prog, &inst->SrcReg[2], c)
[all...] |
| prog_parameter_layout.c | 131 if (inst->SrcReg[i].Base.RelAddr) {
134 if (!inst->SrcReg[i].Symbol->pass1_done) {
137 inst->SrcReg[i].Symbol->param_binding_begin,
138 inst->SrcReg[i].Symbol->param_binding_length);
145 inst->SrcReg[i].Symbol->param_binding_begin = new_begin;
146 inst->SrcReg[i].Symbol->pass1_done = 1;
153 inst->Base.SrcReg[i] = inst->SrcReg[i].Base;
154 inst->Base.SrcReg[i].Index +=
155 inst->SrcReg[i].Symbol->param_binding_begin
[all...] |
| programopt.c | 93 newInst[i].SrcReg[0].File = PROGRAM_STATE_VAR;
94 newInst[i].SrcReg[0].Index = mvpRef[i];
95 newInst[i].SrcReg[0].Swizzle = SWIZZLE_NOOP;
96 newInst[i].SrcReg[1].File = PROGRAM_INPUT;
97 newInst[i].SrcReg[1].Index = VERT_ATTRIB_POS;
98 newInst[i].SrcReg[1].Swizzle = SWIZZLE_NOOP;
164 newInst[0].SrcReg[0].File = PROGRAM_INPUT;
165 newInst[0].SrcReg[0].Index = VERT_ATTRIB_POS;
166 newInst[0].SrcReg[0].Swizzle = SWIZZLE_XXXX;
167 newInst[0].SrcReg[1].File = PROGRAM_STATE_VAR
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_program_tex.c | 70 inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
71 inst_mov->U.I.SrcReg[1].File = RC_FILE_CONSTANT;
72 inst_mov->U.I.SrcReg[1].Index =
76 reset_srcreg(&inst->U.I.SrcReg[0]);
77 inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
78 inst->U.I.SrcReg[0].Index = temp;
93 inst_rcp->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
96 inst_rcp->U.I.SrcReg[0].Swizzle
[all...] |
| radeon_program_alu.c | 45 struct rc_dst_register DstReg, struct rc_src_register SrcReg)
55 fpi->U.I.SrcReg[0] = SrcReg;
73 fpi->U.I.SrcReg[0] = SrcReg0;
74 fpi->U.I.SrcReg[1] = SrcReg1;
93 fpi->U.I.SrcReg[0] = SrcReg0;
94 fpi->U.I.SrcReg[1] = SrcReg1;
95 fpi->U.I.SrcReg[2] = SrcReg2;
131 static struct rc_src_register srcreg(int file, int index) function
208 if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY &
[all...] |
| radeon_optimize.c | 76 &reader_data->Writer->U.I.PreSub.SrcReg[0],
77 &reader_data->Writer->U.I.PreSub.SrcReg[1])) {
91 if(reader_data->Writer->U.I.SrcReg[0].File != RC_FILE_TEMPORARY &&
92 reader_data->Writer->U.I.SrcReg[0].File != RC_FILE_INPUT &&
166 inst->U.I.SrcReg[0].File == RC_FILE_PRESUB ||
167 inst->U.I.SrcReg[0].Abs ||
168 inst->U.I.SrcReg[0].Negate) {
177 *reader_data.Readers[i].U.I.Src = chain_srcregs(*reader_data.Readers[i].U.I.Src, inst_mov->U.I.SrcReg[0]);
179 if (inst_mov->U.I.SrcReg[0].File == RC_FILE_PRESUB)
232 if (is_src_uniform_constant(inst->U.I.SrcReg[2], &swz, &negate))
[all...] |
| radeon_pair_translate.c | 44 inst->SrcReg[2] = inst->SrcReg[1];
45 inst->SrcReg[1].File = RC_FILE_NONE;
46 inst->SrcReg[1].Swizzle = RC_SWIZZLE_1111;
47 inst->SrcReg[1].Negate = RC_MASK_NONE;
51 tmp = inst->SrcReg[2];
52 inst->SrcReg[2] = inst->SrcReg[0];
53 inst->SrcReg[0] = tmp;
66 inst->SrcReg[1].File = RC_FILE_NONE
[all...] |
| r3xx_vertprog.c | 43 (PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[x]), \
48 t_src_class(vpi->SrcReg[x].File), \
49 RC_MASK_NONE) | (vpi->SrcReg[x].RelAddr << 4))
198 inst[1] = t_src(vp, &vpi->SrcReg[0]);
215 inst[1] = t_src(vp, &vpi->SrcReg[0]);
216 inst[2] = t_src(vp, &vpi->SrcReg[1]);
232 inst[1] = t_src_scalar(vp, &vpi->SrcReg[0]);
251 inst[1] = PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[0]), t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 0)), // X
252 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 3)), //
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinInstrInfo.cpp | 102 unsigned DestReg, unsigned SrcReg,
104 if (BF::ALLRegClass.contains(DestReg, SrcReg)) {
106 .addReg(SrcReg, getKillRegState(KillSrc));
110 if (BF::D16RegClass.contains(DestReg, SrcReg)) {
112 .addReg(SrcReg, getKillRegState(KillSrc))
118 if (SrcReg == BF::NCC) {
120 .addReg(SrcReg, getKillRegState(KillSrc));
124 if (SrcReg == BF::CC) {
126 .addReg(SrcReg, getKillRegState(KillSrc));
131 if (BF::DRegClass.contains(SrcReg)) {
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 37 unsigned DestReg, unsigned SrcReg,
40 .addReg(SrcReg, getKillRegState(KillSrc)));
41 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
47 unsigned SrcReg, bool isKill, int FI,
51 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
52 isARMLowRegister(SrcReg))) && "Unknown regclass!");
55 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
56 isARMLowRegister(SrcReg))) {
69 .addReg(SrcReg, getKillRegState(isKill))
|
