| /system/core/libpixelflinger/arch-arm64/ |
| t32cb16blend.S | 52 * clobbered: w6, w7, w16, w17, w18
69 lsr w16, \DREG, #(16 + 11)
70 mul w16, w7, w16
73 add w16, w6, w16, lsr #8
74 cmp w16, #0x1F
76 orr w18, \FB, w16, lsl #(16 + 11)
82 lsr w16, \SRC, #(8+2)
83 and w16, w16, #0x3
[all...] |
| /external/valgrind/VEX/priv/ |
| host_generic_simd128.c | 186 res->w16[0] = max16U(argL->w16[0], argR->w16[0]);
187 res->w16[1] = max16U(argL->w16[1], argR->w16[1]);
188 res->w16[2] = max16U(argL->w16[2], argR->w16[2]);
189 res->w16[3] = max16U(argL->w16[3], argR->w16[3])
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| addsub.d | 8 0: 0b0100f0 add w16, w7, w1
9 4: 0b2100f0 add w16, w7, w1, uxtb
10 8: 0b2100f0 add w16, w7, w1, uxtb
11 c: 0b2104f0 add w16, w7, w1, uxtb #1
12 10: 0b2108f0 add w16, w7, w1, uxtb #2
13 14: 0b210cf0 add w16, w7, w1, uxtb #3
14 18: 0b2110f0 add w16, w7, w1, uxtb #4
15 1c: 0b2120f0 add w16, w7, w1, uxth
16 20: 0b2120f0 add w16, w7, w1, uxth
17 24: 0b2124f0 add w16, w7, w1, uxth #
[all...] |
| /external/boringssl/ios-aarch64/crypto/fipsmodule/ |
| sha256-armv8.S | 60 ldr w16,[x16]
61 tst w16,#ARMV8_SHA256
90 ror w16,w24,#6
98 eor w16,w16,w6,ror#11 // Sigma1(e)
102 add w27,w27,w16 // h+=Sigma1(e)
115 ror w16,w23,#6
123 eor w16,w16,w7,ror#11 // Sigma1(e)
127 add w26,w26,w16 // h+=Sigma1(e
[all...] |
| sha1-armv8.S | 18 ldr w16,[x16]
19 tst w16,#ARMV8_SHA1
205 add w21,w21,w16 // future e+=X[i]
230 eor w3,w3,w16
293 eor w8,w8,w16
362 eor w14,w14,w16
386 eor w16,w16,w19
390 eor w16,w16,w
[all...] |
| /external/boringssl/linux-aarch64/crypto/fipsmodule/ |
| sha256-armv8.S | 61 ldr w16,[x16]
62 tst w16,#ARMV8_SHA256
91 ror w16,w24,#6
99 eor w16,w16,w6,ror#11 // Sigma1(e)
103 add w27,w27,w16 // h+=Sigma1(e)
116 ror w16,w23,#6
124 eor w16,w16,w7,ror#11 // Sigma1(e)
128 add w26,w26,w16 // h+=Sigma1(e
[all...] |
| sha1-armv8.S | 19 ldr w16,[x16]
20 tst w16,#ARMV8_SHA1
206 add w21,w21,w16 // future e+=X[i]
231 eor w3,w3,w16
294 eor w8,w8,w16
363 eor w14,w14,w16
387 eor w16,w16,w19
391 eor w16,w16,w
[all...] |
| /external/llvm/test/MC/Mips/msa/ |
| set-msa-directive.s | 7 # CHECK: addvi.d $w16, $w19, 7
11 # CHECK: subvi.d $w16, $w19, 7
17 addvi.d $w16, $w19, 7
22 subvi.d $w16, $w19, 7
|
| test_3rf.s | 7 # CHECK: fceq.w $w1, $w23, $w16 # encoding: [0x78,0x90,0xb8,0x5a]
8 # CHECK: fceq.d $w0, $w8, $w16 # encoding: [0x78,0xb0,0x40,0x1a]
9 # CHECK: fcle.w $w16, $w9, $w24 # encoding: [0x79,0x98,0x4c,0x1a]
26 # CHECK: fcune.d $w16, $w26, $w21 # encoding: [0x78,0xb5,0xd4,0x1c]
29 # CHECK: fexdo.h $w8, $w0, $w16 # encoding: [0x7a,0x10,0x02,0x1b]
37 # CHECK: fmax_a.w $w10, $w16, $w10 # encoding: [0x7b,0xca,0x82,0x9b]
44 # CHECK: fmsub.d $w8, $w18, $w16 # encoding: [0x79,0x70,0x92,0x1b]
54 # CHECK: fslt.d $w16, $w26, $w21 # encoding: [0x7b,0x35,0xd4,0x1a]
61 # CHECK: fsueq.w $w16, $w24, $w25 # encoding: [0x7a,0xd9,0xc4,0x1a]
69 # CHECK: fsune.w $w16, $w31, $w2 # encoding: [0x7a,0x82,0xfc,0x1c
[all...] |
| test_i8.s | 12 # CHECK: xori.b $w16, $w10, 20 # encoding: [0x7b,0x14,0x54,0x00]
23 xori.b $w16, $w10, 20
|
| test_3r.s | 13 # CHECK: adds_s.w $w16, $w14, $w13 # encoding: [0x79,0x4d,0x74,0x10]
23 # CHECK: asub_s.b $w23, $w16, $w3 # encoding: [0x7a,0x03,0x85,0xd1]
32 # CHECK: ave_s.h $w16, $w19, $w9 # encoding: [0x7a,0x29,0x9c,0x10]
35 # CHECK: ave_u.b $w16, $w19, $w9 # encoding: [0x7a,0x89,0x9c,0x10]
39 # CHECK: aver_s.b $w26, $w16, $w2 # encoding: [0x7b,0x02,0x86,0x90]
48 # CHECK: bclr.h $w16, $w21, $w28 # encoding: [0x79,0xbc,0xac,0x0d]
51 # CHECK: binsl.b $w5, $w16, $w24 # encoding: [0x7b,0x18,0x81,0x4d]
60 # CHECK: bneg.h $w28, $w16, $w4 # encoding: [0x7a,0xa4,0x87,0x0d]
81 # CHECK: clt_s.w $w23, $w8, $w16 # encoding: [0x79,0x50,0x45,0xcf]
84 # CHECK: clt_u.h $w16, $w31, $w23 # encoding: [0x79,0xb7,0xfc,0x0f
[all...] |
| test_i5.s | 6 # CHECK: addvi.d $w16, $w1, 21 # encoding: [0x78,0x75,0x0c,0x06]
11 # CHECK: clei_s.b $w12, $w16, 1 # encoding: [0x7a,0x01,0x83,0x07]
46 # CHECK: subvi.d $w19, $w16, 7 # encoding: [0x78,0xe7,0x84,0xc6]
51 addvi.d $w16, $w1, 21
56 clei_s.b $w12, $w16, 1
91 subvi.d $w19, $w16, 7
|
| test_2r.s | 5 # CHECK: fill.w $w16, $24 # encoding: [0x7b,0x02,0xc4,0x1e]
21 fill.w $w16, $24
|
| /external/llvm/test/MC/Disassembler/Mips/msa/ |
| test_3rf.txt | 7 0x78 0x90 0xb8 0x5a # CHECK: fceq.w $w1, $w23, $w16
8 0x78 0xb0 0x40 0x1a # CHECK: fceq.d $w0, $w8, $w16
9 0x79 0x98 0x4c 0x1a # CHECK: fcle.w $w16, $w9, $w24
26 0x78 0xb5 0xd4 0x1c # CHECK: fcune.d $w16, $w26, $w21
29 0x7a 0x10 0x02 0x1b # CHECK: fexdo.h $w8, $w0, $w16
37 0x7b 0xca 0x82 0x9b # CHECK: fmax_a.w $w10, $w16, $w10
44 0x79 0x70 0x92 0x1b # CHECK: fmsub.d $w8, $w18, $w16
54 0x7b 0x35 0xd4 0x1a # CHECK: fslt.d $w16, $w26, $w21
61 0x7a 0xd9 0xc4 0x1a # CHECK: fsueq.w $w16, $w24, $w25
69 0x7a 0x82 0xfc 0x1c # CHECK: fsune.w $w16, $w31, $w
[all...] |
| test_3r.txt | 13 0x79 0x4d 0x74 0x10 # CHECK: adds_s.w $w16, $w14, $w13
23 0x7a 0x03 0x85 0xd1 # CHECK: asub_s.b $w23, $w16, $w3
32 0x7a 0x29 0x9c 0x10 # CHECK: ave_s.h $w16, $w19, $w9
35 0x7a 0x89 0x9c 0x10 # CHECK: ave_u.b $w16, $w19, $w9
39 0x7b 0x02 0x86 0x90 # CHECK: aver_s.b $w26, $w16, $w2
48 0x79 0xbc 0xac 0x0d # CHECK: bclr.h $w16, $w21, $w28
51 0x7b 0x18 0x81 0x4d # CHECK: binsl.b $w5, $w16, $w24
60 0x7a 0xa4 0x87 0x0d # CHECK: bneg.h $w28, $w16, $w4
81 0x79 0x50 0x45 0xcf # CHECK: clt_s.w $w23, $w8, $w16
84 0x79 0xb7 0xfc 0x0f # CHECK: clt_u.h $w16, $w31, $w2
[all...] |
| test_i8.txt | 12 0x7b 0x14 0x54 0x00 # CHECK: xori.b $w16, $w10, 20
|
| /external/llvm/test/MC/AArch64/ |
| arm64-basic-a64-instructions.s | 10 crc32cx w18, w16, xzr
18 // CHECK: crc32cx w18, w16, xzr // encoding: [0x12,0x5e,0xdf,0x9a]
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| msa.s | 12 slli.h $w16,$w17,0
26 srai.w $w16,$w17,0
40 srli.d $w16,$w17,0
54 bset.b $w16,$w17,$w18
67 bneg.h $w15,$w16,$w17
80 binsl.w $w14,$w15,$w16
94 binsri.b $w16,$w17,0
108 addvi.h $w16,$w17,0
122 subvi.w $w16,$w17,0
136 maxi_s.d $w16,$w17,-1
[all...] |
| msa-relax.s | 22 bnz.w $w16, foo
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-crc32.txt | 10 # CHECK: crc32cx w18, w16, xzr
|
| /toolchain/binutils/binutils-2.25/gas/doc/ |
| h8.texi | 20 @set W16
|
| /system/core/libpixelflinger/tests/arch-arm64/disassembler/ |
| arm64_diassembler_test.cpp | 55 { 0x4b1e0200, "sub w0, w16, w30, lsl #0" },
56 { 0x4b507fdf, "sub wzr, w30, w16, lsr #31" },
57 { 0x4b8043f0, "sub w16, wzr, w0, asr #16" },
60 { 0x6b1e0200, "subs w0, w16, w30, lsl #0" },
61 { 0x6b507fdf, "subs wzr, w30, w16, lsr #31" },
62 { 0x6b8043f0, "subs w16, wzr, w0, asr #16" },
65 { 0x0a1e0200, "and w0, w16, w30, lsl #0" },
66 { 0x0a507fdf, "and wzr, w30, w16, lsr #31" },
67 { 0x0a8043f0, "and w16, wzr, w0, asr #16" },
70 { 0x2a1e0200, "orr w0, w16, w30, lsl #0" }
[all...] |
| /external/boringssl/ios-aarch64/crypto/chacha/ |
| chacha-armv8.S | 101 add w16,w16,w21
105 eor w12,w12,w16
125 add w16,w16,w21
129 eor w12,w12,w16
147 add w16,w16,w17
151 eor w11,w11,w16
171 add w16,w16,w1
[all...] |
| /external/boringssl/linux-aarch64/crypto/chacha/ |
| chacha-armv8.S | 102 add w16,w16,w21
106 eor w12,w12,w16
126 add w16,w16,w21
130 eor w12,w12,w16
148 add w16,w16,w17
152 eor w11,w11,w16
172 add w16,w16,w1
[all...] |
| /art/compiler/utils/mips64/ |
| managed_register_mips64_test.cc | 293 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
311 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
315 reg_o = Mips64ManagedRegister::FromVectorRegister(W16);
322 EXPECT_EQ(W16, reg.AsOverlappingVectorRegister());
329 EXPECT_TRUE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
347 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
365 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
383 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromVectorRegister(W16)));
386 reg = Mips64ManagedRegister::FromVectorRegister(W16);
393 EXPECT_EQ(W16, reg_o.AsOverlappingVectorRegister())
[all...] |
