1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X32 3 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X32 4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64 5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X64 6 7 define <2 x double> @fabs_v2f64(<2 x double> %p) { 8 ; X32-LABEL: fabs_v2f64: 9 ; X32: # BB#0: 10 ; X32-NEXT: vandpd .LCPI0_0, %xmm0, %xmm0 11 ; X32-NEXT: retl 12 ; 13 ; X64-LABEL: fabs_v2f64: 14 ; X64: # BB#0: 15 ; X64-NEXT: vandpd {{.*}}(%rip), %xmm0, %xmm0 16 ; X64-NEXT: retq 17 %t = call <2 x double> @llvm.fabs.v2f64(<2 x double> %p) 18 ret <2 x double> %t 19 } 20 declare <2 x double> @llvm.fabs.v2f64(<2 x double> %p) 21 22 define <4 x float> @fabs_v4f32(<4 x float> %p) { 23 ; X32-LABEL: fabs_v4f32: 24 ; X32: # BB#0: 25 ; X32-NEXT: vandps .LCPI1_0, %xmm0, %xmm0 26 ; X32-NEXT: retl 27 ; 28 ; X64-LABEL: fabs_v4f32: 29 ; X64: # BB#0: 30 ; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 31 ; X64-NEXT: retq 32 %t = call <4 x float> @llvm.fabs.v4f32(<4 x float> %p) 33 ret <4 x float> %t 34 } 35 declare <4 x float> @llvm.fabs.v4f32(<4 x float> %p) 36 37 define <4 x double> @fabs_v4f64(<4 x double> %p) { 38 ; X32-LABEL: fabs_v4f64: 39 ; X32: # BB#0: 40 ; X32-NEXT: vandpd .LCPI2_0, %ymm0, %ymm0 41 ; X32-NEXT: retl 42 ; 43 ; X64-LABEL: fabs_v4f64: 44 ; X64: # BB#0: 45 ; X64-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm0 46 ; X64-NEXT: retq 47 %t = call <4 x double> @llvm.fabs.v4f64(<4 x double> %p) 48 ret <4 x double> %t 49 } 50 declare <4 x double> @llvm.fabs.v4f64(<4 x double> %p) 51 52 define <8 x float> @fabs_v8f32(<8 x float> %p) { 53 ; X32-LABEL: fabs_v8f32: 54 ; X32: # BB#0: 55 ; X32-NEXT: vandps .LCPI3_0, %ymm0, %ymm0 56 ; X32-NEXT: retl 57 ; 58 ; X64-LABEL: fabs_v8f32: 59 ; X64: # BB#0: 60 ; X64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 61 ; X64-NEXT: retq 62 %t = call <8 x float> @llvm.fabs.v8f32(<8 x float> %p) 63 ret <8 x float> %t 64 } 65 declare <8 x float> @llvm.fabs.v8f32(<8 x float> %p) 66 67 ; PR20354: when generating code for a vector fabs op, 68 ; make sure that we're only turning off the sign bit of each float value. 69 ; No constant pool loads or vector ops are needed for the fabs of a 70 ; bitcasted integer constant; we should just return an integer constant 71 ; that has the sign bits turned off. 72 ; 73 ; So instead of something like this: 74 ; movabsq (constant pool load of mask for sign bits) 75 ; vmovq (move from integer register to vector/fp register) 76 ; vandps (mask off sign bits) 77 ; vmovq (move vector/fp register back to integer return register) 78 ; 79 ; We should generate: 80 ; mov (put constant value in return register) 81 82 define i64 @fabs_v2f32_1() { 83 ; X32-LABEL: fabs_v2f32_1: 84 ; X32: # BB#0: 85 ; X32-NEXT: xorl %eax, %eax 86 ; X32-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF 87 ; X32-NEXT: retl 88 ; 89 ; X64-LABEL: fabs_v2f32_1: 90 ; X64: # BB#0: 91 ; X64-NEXT: movabsq $9223372032559808512, %rax # imm = 0x7FFFFFFF00000000 92 ; X64-NEXT: retq 93 %bitcast = bitcast i64 18446744069414584320 to <2 x float> ; 0xFFFF_FFFF_0000_0000 94 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %bitcast) 95 %ret = bitcast <2 x float> %fabs to i64 96 ret i64 %ret 97 } 98 99 define i64 @fabs_v2f32_2() { 100 ; X32-LABEL: fabs_v2f32_2: 101 ; X32: # BB#0: 102 ; X32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 103 ; X32-NEXT: xorl %edx, %edx 104 ; X32-NEXT: retl 105 ; 106 ; X64-LABEL: fabs_v2f32_2: 107 ; X64: # BB#0: 108 ; X64-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF 109 ; X64-NEXT: retq 110 %bitcast = bitcast i64 4294967295 to <2 x float> ; 0x0000_0000_FFFF_FFFF 111 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %bitcast) 112 %ret = bitcast <2 x float> %fabs to i64 113 ret i64 %ret 114 } 115 116 declare <2 x float> @llvm.fabs.v2f32(<2 x float> %p) 117
