Lines Matching refs:rd
99 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd,
103 CHECK_NE(rd, kNoGpuRegister);
107 static_cast<uint32_t>(rd) << kRdShift |
113 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd,
116 CHECK_NE(rd, kNoGpuRegister);
120 static_cast<uint32_t>(rd) << kRdShift |
126 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd,
129 CHECK_NE(rd, kNoGpuRegister);
133 static_cast<uint32_t>(rd) << kRdShift |
303 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
304 EmitR(0, rs, rt, rd, 0, 0x21);
311 void Mips64Assembler::Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
312 EmitR(0, rs, rt, rd, 0, 0x2d);
319 void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
320 EmitR(0, rs, rt, rd, 0, 0x23);
323 void Mips64Assembler::Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
324 EmitR(0, rs, rt, rd, 0, 0x2f);
327 void Mips64Assembler::MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
328 EmitR(0, rs, rt, rd, 2, 0x18);
331 void Mips64Assembler::MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
332 EmitR(0, rs, rt, rd, 3, 0x18);
335 void Mips64Assembler::DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
336 EmitR(0, rs, rt, rd, 2, 0x1a);
339 void Mips64Assembler::ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
340 EmitR(0, rs, rt, rd, 3, 0x1a);
343 void Mips64Assembler::DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
344 EmitR(0, rs, rt, rd, 2, 0x1b);
347 void Mips64Assembler::ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
348 EmitR(0, rs, rt, rd, 3, 0x1b);
351 void Mips64Assembler::Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
352 EmitR(0, rs, rt, rd, 2, 0x1c);
355 void Mips64Assembler::Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
356 EmitR(0, rs, rt, rd, 3, 0x1c);
359 void Mips64Assembler::Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
360 EmitR(0, rs, rt, rd, 2, 0x1e);
363 void Mips64Assembler::Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
364 EmitR(0, rs, rt, rd, 3, 0x1e);
367 void Mips64Assembler::Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
368 EmitR(0, rs, rt, rd, 2, 0x1f);
371 void Mips64Assembler::Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
372 EmitR(0, rs, rt, rd, 3, 0x1f);
375 void Mips64Assembler::And(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
376 EmitR(0, rs, rt, rd, 0, 0x24);
383 void Mips64Assembler::Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
384 EmitR(0, rs, rt, rd, 0, 0x25);
391 void Mips64Assembler::Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
392 EmitR(0, rs, rt, rd, 0, 0x26);
399 void Mips64Assembler::Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
400 EmitR(0, rs, rt, rd, 0, 0x27);
403 void Mips64Assembler::Bitswap(GpuRegister rd, GpuRegister rt) {
404 EmitRtd(0x1f, rt, rd, 0x0, 0x20);
407 void Mips64Assembler::Dbitswap(GpuRegister rd, GpuRegister rt) {
408 EmitRtd(0x1f, rt, rd, 0x0, 0x24);
411 void Mips64Assembler::Seb(GpuRegister rd, GpuRegister rt) {
412 EmitR(0x1f, static_cast<GpuRegister>(0), rt, rd, 0x10, 0x20);
415 void Mips64Assembler::Seh(GpuRegister rd, GpuRegister rt) {
416 EmitR(0x1f, static_cast<GpuRegister>(0), rt, rd, 0x18, 0x20);
419 void Mips64Assembler::Dsbh(GpuRegister rd, GpuRegister rt) {
420 EmitRtd(0x1f, rt, rd, 0x2, 0x24);
423 void Mips64Assembler::Dshd(GpuRegister rd, GpuRegister rt) {
424 EmitRtd(0x1f, rt, rd, 0x5, 0x24);
433 void Mips64Assembler::Ins(GpuRegister rd, GpuRegister rt, int pos, int size) {
437 EmitR(0x1f, rt, rd, static_cast<GpuRegister>(pos + size - 1), pos, 0x04);
471 void Mips64Assembler::Lsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne) {
474 EmitR(0x0, rs, rt, rd, sa, 0x05);
477 void Mips64Assembler::Dlsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne) {
480 EmitR(0x0, rs, rt, rd, sa, 0x15);
483 void Mips64Assembler::Wsbh(GpuRegister rd, GpuRegister rt) {
484 EmitRtd(0x1f, rt, rd, 2, 0x20);
507 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) {
508 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00);
511 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) {
512 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x02);
515 void Mips64Assembler::Rotr(GpuRegister rd, GpuRegister rt, int shamt) {
516 EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x02);
519 void Mips64Assembler::Sra(GpuRegister rd, GpuRegister rt, int shamt) {
520 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x03);
523 void Mips64Assembler::Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
524 EmitR(0, rs, rt, rd, 0, 0x04);
527 void Mips64Assembler::Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
528 EmitR(0, rs, rt, rd, 1, 0x06);
531 void Mips64Assembler::Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
532 EmitR(0, rs, rt, rd, 0, 0x06);
535 void Mips64Assembler::Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
536 EmitR(0, rs, rt, rd, 0, 0x07);
539 void Mips64Assembler::Dsll(GpuRegister rd, GpuRegister rt, int shamt) {
540 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x38);
543 void Mips64Assembler::Dsrl(GpuRegister rd, GpuRegister rt, int shamt) {
544 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3a);
547 void Mips64Assembler::Drotr(GpuRegister rd, GpuRegister rt, int shamt) {
548 EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x3a);
551 void Mips64Assembler::Dsra(GpuRegister rd, GpuRegister rt, int shamt) {
552 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3b);
555 void Mips64Assembler::Dsll32(GpuRegister rd, GpuRegister rt, int shamt) {
556 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3c);
559 void Mips64Assembler::Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) {
560 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3e);
563 void Mips64Assembler::Drotr32(GpuRegister rd, GpuRegister rt, int shamt) {
564 EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x3e);
567 void Mips64Assembler::Dsra32(GpuRegister rd, GpuRegister rt, int shamt) {
568 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3f);
571 void Mips64Assembler::Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
572 EmitR(0, rs, rt, rd, 0, 0x14);
575 void Mips64Assembler::Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
576 EmitR(0, rs, rt, rd, 0, 0x16);
579 void Mips64Assembler::Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
580 EmitR(0, rs, rt, rd, 1, 0x16);
583 void Mips64Assembler::Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
584 EmitR(0, rs, rt, rd, 0, 0x17);
672 void Mips64Assembler::Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
673 EmitR(0, rs, rt, rd, 0, 0x2a);
676 void Mips64Assembler::Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
677 EmitR(0, rs, rt, rd, 0, 0x2b);
688 void Mips64Assembler::Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
689 EmitR(0, rs, rt, rd, 0, 0x35);
692 void Mips64Assembler::Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
693 EmitR(0, rs, rt, rd, 0, 0x37);
696 void Mips64Assembler::Clz(GpuRegister rd, GpuRegister rs) {
697 EmitRsd(0, rs, rd, 0x01, 0x10);
700 void Mips64Assembler::Clo(GpuRegister rd, GpuRegister rs) {
701 EmitRsd(0, rs, rd, 0x01, 0x11);
704 void Mips64Assembler::Dclz(GpuRegister rd, GpuRegister rs) {
705 EmitRsd(0, rs, rd, 0x01, 0x12);
708 void Mips64Assembler::Dclo(GpuRegister rd, GpuRegister rs) {
709 EmitRsd(0, rs, rd, 0x01, 0x13);
712 void Mips64Assembler::Jalr(GpuRegister rd, GpuRegister rs) {
713 EmitR(0, rs, static_cast<GpuRegister>(0), rd, 0, 0x09);
1315 void Mips64Assembler::Move(GpuRegister rd, GpuRegister rs) {
1316 Or(rd, rs, ZERO);
1319 void Mips64Assembler::Clear(GpuRegister rd) {
1320 Move(rd, ZERO);
1323 void Mips64Assembler::Not(GpuRegister rd, GpuRegister rs) {
1324 Nor(rd, rs, ZERO);
1948 void Mips64Assembler::Copy_sB(GpuRegister rd, VectorRegister ws, int n4) {
1951 EmitMsaELM(0x2, n4 | kMsaDfNByteMask, ws, static_cast<VectorRegister>(rd), 0x19);
1954 void Mips64Assembler::Copy_sH(GpuRegister rd, VectorRegister ws, int n3) {
1957 EmitMsaELM(0x2, n3 | kMsaDfNHalfwordMask, ws, static_cast<VectorRegister>(rd), 0x19);
1960 void Mips64Assembler::Copy_sW(GpuRegister rd, VectorRegister ws, int n2) {
1963 EmitMsaELM(0x2, n2 | kMsaDfNWordMask, ws, static_cast<VectorRegister>(rd), 0x19);
1966 void Mips64Assembler::Copy_sD(GpuRegister rd, VectorRegister ws, int n1) {
1969 EmitMsaELM(0x2, n1 | kMsaDfNDoublewordMask, ws, static_cast<VectorRegister>(rd), 0x19);
1972 void Mips64Assembler::Copy_uB(GpuRegister rd, VectorRegister ws, int n4) {
1975 EmitMsaELM(0x3, n4 | kMsaDfNByteMask, ws, static_cast<VectorRegister>(rd), 0x19);
1978 void Mips64Assembler::Copy_uH(GpuRegister rd, VectorRegister ws, int n3) {
1981 EmitMsaELM(0x3, n3 | kMsaDfNHalfwordMask, ws, static_cast<VectorRegister>(rd), 0x19);
1984 void Mips64Assembler::Copy_uW(GpuRegister rd, VectorRegister ws, int n2) {
1987 EmitMsaELM(0x3, n2 | kMsaDfNWordMask, ws, static_cast<VectorRegister>(rd), 0x19);
2293 void Mips64Assembler::LoadConst32(GpuRegister rd, int32_t value) {
2294 TemplateLoadConst32(this, rd, value);
2301 void Mips64Assembler::LoadConst64(GpuRegister rd, int64_t value) {
2302 TemplateLoadConst64(this, rd, value);
