Lines Matching full:mips64
24 #include "arch/mips64/instruction_set_features_mips64.h"
39 namespace mips64 {
448 void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
449 void Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64
451 void Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
459 void Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
460 void Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
461 void Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
462 void Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
463 void Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
464 void Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
475 void Dbitswap(GpuRegister rd, GpuRegister rt); // MIPS64
478 void Dsbh(GpuRegister rd, GpuRegister rt); // MIPS64
479 void Dshd(GpuRegister rd, GpuRegister rt); // MIPS64
480 void Dext(GpuRegister rs, GpuRegister rt, int pos, int size); // MIPS64
482 void Dins(GpuRegister rt, GpuRegister rs, int pos, int size); // MIPS64
483 void Dinsm(GpuRegister rt, GpuRegister rs, int pos, int size); // MIPS64
484 void Dinsu(GpuRegister rt, GpuRegister rs, int pos, int size); // MIPS64
485 void DblIns(GpuRegister rt, GpuRegister rs, int pos, int size); // MIPS64
487 void Dlsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne); // MIPS64
490 void Scd(GpuRegister rt, GpuRegister base, int16_t imm9 = 0); // MIPS64
492 void Lld(GpuRegister rt, GpuRegister base, int16_t imm9 = 0); // MIPS64
502 void Dsll(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
503 void Dsrl(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
504 void Drotr(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
505 void Dsra(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
506 void Dsll32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
507 void Dsrl32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
508 void Drotr32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
509 void Dsra32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
510 void Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs); // MIPS64
511 void Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs); // MIPS64
512 void Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs); // MIPS64
513 void Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs); // MIPS64
518 void Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64
521 void Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64
523 void Lwupc(GpuRegister rs, uint32_t imm19); // MIPS64
524 void Ldpc(GpuRegister rs, uint32_t imm18); // MIPS64
527 void Daui(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64
528 void Dahi(GpuRegister rs, uint16_t imm16); // MIPS64
529 void Dati(GpuRegister rs, uint16_t imm16); // MIPS64
535 void Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64
545 void Dclz(GpuRegister rd, GpuRegister rs); // MIPS64
546 void Dclo(GpuRegister rd, GpuRegister rs); // MIPS64
658 void Dmfc1(GpuRegister rt, FpuRegister fs); // MIPS64
659 void Dmtc1(GpuRegister rt, FpuRegister fs); // MIPS64
872 void LoadConst64(GpuRegister rd, int64_t value); // MIPS64
878 void Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp = AT); // MIPS64
922 UNIMPLEMENTED(FATAL) << "Do not use Jump for MIPS64";
933 LOG(FATAL) << "Not implemented on MIPS64";
938 LOG(FATAL) << "Not implemented on MIPS64";
945 LOG(FATAL) << "Not implemented on MIPS64";
951 LOG(FATAL) << "Not implemented on MIPS64";
1728 } // namespace mips64
