Lines Matching refs:rd
66 void TemplateLoadConst32(Asm* a, GpuRegister rd, int32_t value) {
69 a->Ori(rd, ZERO, value);
72 a->Addiu(rd, ZERO, value);
76 a->Lui(rd, value >> 16);
80 a->Ori(rd, rd, value);
97 void TemplateLoadConst64(Asm* a, Rtype rd, Vtype value) {
105 a->Ori(rd, ZERO, value);
109 a->Daddiu(rd, ZERO, value);
114 a->Lui(rd, value >> 16);
120 a->Lui(rd, value >> 16);
121 a->Ori(rd, rd, value);
127 a->Ori(rd, ZERO, value);
128 a->Dahi(rd, value >> 32);
134 a->Ori(rd, ZERO, value);
135 a->Dati(rd, value >> 48);
141 a->Lui(rd, value >> 16);
142 a->Dahi(rd, (value >> 32) + bit31);
148 a->Lui(rd, value >> 16);
149 a->Dati(rd, (value >> 48) + bit31);
155 a->Daddiu(rd, ZERO, value);
156 a->Dahi(rd, (value >> 32) + bit31);
162 a->Daddiu(rd, ZERO, value);
163 a->Dati(rd, (value >> 48) + bit31);
169 a->Daddiu(rd, ZERO, -1);
171 a->Dsrl(rd, rd, shift_cnt);
173 a->Dsrl32(rd, rd, shift_cnt & 31);
182 a->Ori(rd, ZERO, tmp);
184 a->Dsll(rd, rd, shift_cnt);
186 a->Dsll32(rd, rd, shift_cnt & 31);
192 a->Daddiu(rd, ZERO, tmp);
194 a->Dsll(rd, rd, shift_cnt);
196 a->Dsll32(rd, rd, shift_cnt & 31);
202 a->LoadConst32(rd, value);
203 a->Dinsu(rd, rd, 32, 32);
210 a->Lui(rd, tmp >> 16);
211 a->Ori(rd, rd, tmp);
213 a->Dsll(rd, rd, shift_cnt);
215 a->Dsll32(rd, rd, shift_cnt & 31);
224 a->Ori(rd, ZERO, tmp);
226 a->Dsll(rd, rd, shift_cnt);
228 a->Dsll32(rd, rd, shift_cnt & 31);
230 a->Ori(rd, rd, value);
235 a->Daddiu(rd, ZERO, tmp);
237 a->Dsll(rd, rd, shift_cnt);
239 a->Dsll32(rd, rd, shift_cnt & 31);
241 a->Ori(rd, rd, value);
245 a->LoadConst32(rd, value);
246 a->Dinsu(rd, rd, 32, 32);
254 a->LoadConst32(rd, value);
259 a->Dahi(rd, tmp2 >> 32);
265 a->Dati(rd, tmp2 >> 48);
446 void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
448 void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
450 void Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
451 void Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
453 void MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
454 void MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
455 void DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
456 void ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
457 void DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
458 void ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
459 void Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
460 void Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
461 void Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
462 void Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
463 void Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
464 void Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
466 void And(GpuRegister rd, GpuRegister rs, GpuRegister rt);
468 void Or(GpuRegister rd, GpuRegister rs, GpuRegister rt);
470 void Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt);
472 rd, GpuRegister rs, GpuRegister rt);
474 void Bitswap(GpuRegister rd, GpuRegister rt);
475 void Dbitswap(GpuRegister rd, GpuRegister rt); // MIPS64
476 void Seb(GpuRegister rd, GpuRegister rt);
477 void Seh(GpuRegister rd, GpuRegister rt);
478 void Dsbh(GpuRegister rd, GpuRegister rt); // MIPS64
479 void Dshd(GpuRegister rd, GpuRegister rt); // MIPS64
486 void Lsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne);
487 void Dlsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne); // MIPS64
488 void Wsbh(GpuRegister rd, GpuRegister rt);
494 void Sll(GpuRegister rd, GpuRegister rt, int shamt);
495 void Srl(GpuRegister rd, GpuRegister rt, int shamt);
496 void Rotr(GpuRegister rd, GpuRegister rt, int shamt);
497 void Sra(GpuRegister rd, GpuRegister rt, int shamt);
498 void Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
499 void Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
500 void Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
501 void Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs);
502 void Dsll(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
503 void Dsrl(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
504 void Drotr(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
505 void Dsra(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
506 void Dsll32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
507 void Dsrl32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
508 void Drotr32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
509 void Dsra32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
510 void Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs); // MIPS64
511 void Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs); // MIPS64
512 void Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs); // MIPS64
513 void Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs); // MIPS64
537 void Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt);
538 void Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
541 void Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt);
542 void Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt);
543 void Clz(GpuRegister rd, GpuRegister rs);
544 void Clo(GpuRegister rd, GpuRegister rs);
545 void Dclz(GpuRegister rd, GpuRegister rs); // MIPS64
546 void Dclo(GpuRegister rd, GpuRegister rs); // MIPS64
548 void Jalr(GpuRegister rd, GpuRegister rs);
667 void Move(GpuRegister rd, GpuRegister rs);
668 void Clear(GpuRegister rd);
669 void Not(GpuRegister rd, GpuRegister rs);
800 void Copy_sB(GpuRegister rd, VectorRegister ws, int n4);
801 void Copy_sH(GpuRegister rd, VectorRegister ws, int n3);
802 void Copy_sW(GpuRegister rd, VectorRegister ws, int n2);
803 void Copy_sD(GpuRegister rd, VectorRegister ws, int n1);
804 void Copy_uB(GpuRegister rd, VectorRegister ws, int n4);
805 void Copy_uH(GpuRegister rd, VectorRegister ws, int n3);
806 void Copy_uW(GpuRegister rd, VectorRegister ws, int n2);
871 void LoadConst32(GpuRegister rd, int32_t value);
872 void LoadConst64(GpuRegister rd, int64_t value); // MIPS64
1649 void EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, int shamt, int funct);
1650 void EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, int shamt, int funct);
1651 void EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, int shamt, int funct);
