Lines Matching refs:MPU
221 - Core MPU Register
503 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
504 \brief Type definitions for the Memory Protection Unit (MPU)
508 /** \brief Structure type to access the Memory Protection Unit (MPU).
512 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
513 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
514 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
515 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
516 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
519 /* MPU Type Register */
520 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
521 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
523 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
524 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
526 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
527 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
529 /* MPU Control Register */
530 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
531 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
533 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
534 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
536 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
537 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
539 /* MPU Region Number Register */
540 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
541 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
543 /* MPU Region Base Address Register */
544 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
545 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
547 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
548 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
550 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
551 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
553 /* MPU Region Attribute and Size Register */
554 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
555 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
557 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
558 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
560 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
561 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
563 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
564 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
566 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
567 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
569 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
570 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
572 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
573 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
575 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
576 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
578 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
579 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
581 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
582 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
616 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
